DP83825I: What voltage node is RST_N terminal internal pull up connected to?

Hi Alvaro,

Thank you very much for your reply.

1.8V is applied to VDDIO pin in their evaluation. They measured RST_N pin voltage when VDDA3V3 is 3.3V. As the result, RST_N was 3.3V (RST_N was floating). So they think RST_N pull up circuit is connected to VDDA3V3.

Which is correct, RST_N pull up is connected to VDDA3V3 or VDDIO?

Thank you again and best regards,
Kazuya.

Hi Alvaro,

Thank you very much for the information.

Will you change  RESET_N input voltage range spec like the follow for the next datasheet version?

Recommended Operating Conditions

                   Min                         Typ                Max
RESET_N : AVDD3V3-10%     AVDD3V3     AVDD3V3+10%

AVDD3V3 voltage range is 3V~3.6V.
So I think RESET_N voltage range is 2.7V(3.0V*90%) ~ 3.96V(3.6V*110%).

Is my understanding correct?

Thank you again and best regards,
Kazuya.

Hi Alvaro,

I'm sorry I had mis-type in the previous reply. The following is correct.

                   Min                         Typ                Max
RESET_N : VDDA3V3-10%     VDDA3V3     VDDA3V3+10%

Is my understanding correct?

Thank you again and best regards,
Kazuya.

Hi Alvaro,

Could I ask you an additional question as the follow?

Q. 
Is RESET_N threshold voltage not changed?
The signal low threshold is 0.35*VDDIO(Max).
 The signal high threshold is 0.65*VDDIO(Min).
Are these threshold not change? Because they drive RESET_N pin by 1.8V output port of MCU with VDDIO=1.8V.

Could you give me your reply?

Thank you and best regards,
Kazuya. 

Hi Alvaro,

Thank you very much for your reply.

Please let me confirm.
Do you mean that VIH and VIL of RESET_N pin are not changed from 1.7V(Min) and 0.8V(Max) not depend on VDDIO applied voltage? They apply 1.8V to VDDIO pin.

Thank you again and best regards,
Kazuya.