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DS90UH929-Q1: DS90UH929/928 tentative black screen issue debug

Part Number: DS90UH929-Q1
Other Parts Discussed in Thread: ALP

Hello expert,

Our customer is facing unexpected tentative black screen issue with DS90UH929/928.
For debugging this phenomena, would you answer following questions?

  1. Is there any other problem which case lock loss from the view point of 929 and 928 system?
    1. Channel specification (return loss, insertion loss, cross talk, etc violations)
    2. HDMI CLK input stability and jitter specifications
    3. Power supply stability and noise specifications
    4. Power sequencing issues
  2. What problem will cause lock loss from DES side?
  3. Is there any way to confirm the correlation between IN_CLK halting and Lock Loss except directly monitoring IN_CLK and LOCK pin as follows.
  4. Is there any way to monitor 929's specific bit on 0x0C or 0x5A through GPIO or INTB?

Best regards,
Kazuki Kuramochi

  • Hi Kazuki,

    Is there any other problem which case lock loss from the view point of 929 and 928 system?

    No, you covered the major cases.

    What problem will cause lock loss from DES side?

    The DES will look for a specific data sequence in the forward channel frame for lock. Any disturbance to this data sequence (for example, loose connection, high jitter, VOD change) could cause lock drop - Further discussion need to be taken offline.  I will reach out to you over email with more details.

    Is there any way to confirm the correlation between IN_CLK halting and Lock Loss except directly monitoring IN_CLK and LOCK pin as follows.

    You can use internal patgen with external timing and internal patgen with internal timing, that way you can isolate whether the issue is due to timing or clk. 

    In addition, you can check the following:

    • MAP tool result measured from deserializer within ALP. See userguide here: https://www.ti.com/lit/ug/snlu243/snlu243.pdf
    • Measure total channel return and insertion loss and check against channel specification
    • Measure HDMI CLK jitter and clock stability meets datasheet specification
      • This requires special scope settings to match CDR PLL, see below:
      • To characterize total jitter, TI recommends to measure the TJ@BER with a high speed oscilloscope equipped with a jitter analysis program such as DPOJET. The clock recovery settings used in the DPOJET measurement are designed to match the input PLL characteristic of the serializer device

        - Method = PLL Custom BW

        - PLL Type = Type II

        - Loop BW = 1MHz

        - Damping = 700m

        - Target BER = 1e-10

        - High pass filter: None

        - Low pass filter: None

    Is there any way to monitor 929's specific bit on 0x0C or 0x5A through GPIO or INTB?

    No, but can you provide register dumps from both devices during the error case and during normal operations. Please provide these in text form not as screenshot so that I can compare them.

    Regards,
    Fadi A.

  • Hello Fadi,

    Thank you for your kindly explanation.
    As I explained in mail, my customer is only covered at DES side.

    Therefore, I'll talk with customer about how to proceed your suggested debug with other customer.

    Best regards.
    Kazuki Kuramochi