XIO2001: Power-Down Sequence

Shota Kobayashi

Prodigy 30 points

Part Number: XIO2001

Hi Team,

Please tell me about the Power-Down Sequence of the XIO 2001.

The data sheet states that power must be removed after asserting PERST # and stopping REFCLK.

However, in our design, Vdd_33 starts falling down about 90us faster than PERST # and REFCLK.

Can this damage the XIO2001?

*From the following thread, it was recognized that there is no problem to assert PERST # and stop REFCLK at the same time.

e2e.ti.com/.../xio2001-power-down-sequence-query-modifications

Best Regards,

Kobayashi

over 1 year ago

0 David Waier over 1 year ago

TI__Genius 14616 points

Hi Shota-san,

Please refer to the following thread as well regarding power-down sequencing: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/727336/xio2001-power-up-sequence-pcir

Recommendation would be to follow data sheet guidelines outlined in section 6.12.2. It must also be ensured that PCIR (clamp voltage) is removed properly.

Best,
David

0 Shota Kobayashi over 1 year ago in reply to David Waier

Prodigy 30 points

Hi David,

Thank you for your reply.

I read the thread you told me about.

The PCIR is connected to Vdd_33 through 1 kΩ, as shown in the UserGuide. (The PCI bus voltage is +3.3 V.)

Therefore, in the Power-Down Sequence, the PCIR begins to fall at about the same time as Vdd_33.

Is this also not recommended because the removal of PCIR is not before the removal of Vdd_ 33?

What kind of problems might occur with a sequence like our waveform?

Best Regards,

Kobayashi

0 David Waier over 1 year ago in reply to Shota Kobayashi

TI__Genius 14616 points

Hi Shota-san,

The configuration you have described in your board sounds sufficient. As long as you are following the recommendations in the data sheet and EVM User's guide, problems would not occur.

The PCIR rail would ideally be removed before the removal of VDD_33 and VDD_15 in order to protect the I/O cells of the PCI bus.

Best,
David

0 Shota Kobayashi over 1 year ago in reply to David Waier

Prodigy 30 points

Hi David,

I understand that the PCIR connection is fine because it follows the datasheet and EVM User Guide.
As for Vdd_33 and PCIR starting to drop about 90 microseconds earlier than PERST# and REFCLK, can you tell me what kind of problem it causes?
I am concerned about the impact because if a fatal problem is expected, we need to consider changing the circuit.

Best Regards,
Kobayashi

0 David Waier over 1 year ago in reply to Shota Kobayashi

TI__Genius 14616 points

Hi Shota-san,

The potential problem from this timing could be damage to PCI bus I/O cells. The scale of this impact is difficult to quantify.

Best,
David

0 Shota Kobayashi over 1 year ago in reply to David Waier

Prodigy 30 points

Hi David,

Since the capacitor (0.1μF) is attached to the PCIR pin according to the EVM User's Guide, the PCIR actually falls a little more slowly than Vdd_33.
The waveforms we measured are shown below.

If the PCIR is +3.0 V when the PERST# assertion and REFCLK are removed, does this mean that the maximum input voltage on the PCI bus is PCIR+0.5=3.5V according to the Absolute Maximum Ratings on the datasheet, and that no damage to the PCI bus I/O cells occurs on a +3.3V PCI bus?

Best Regards,
Kobayashi

+1 David Waier over 1 year ago in reply to Shota Kobayashi

TI__Genius 14616 points

Hi Shota-san,

Correct. As long as the absolute maximum ratings are not violated, damage will not occur.

Best,
David

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XIO2001: Power-Down Sequence