DS25BR100 / DS25BR101 input capacitance

Sergey Kolen

Prodigy 20 points

Other Parts Discussed in Thread: DS25BR101, DS25BR100

Hi,

I would like to figure our my problem.

I have LVDS transmitter that promise high speed LVDS rate (2Gbps) only for receiver that has input capacitance <2pF.

the problem that my receiver (FPGA) has input capacitance of ~8pF.

I think to implement your buffer DS25BR100 / DS25BR101 , as I see this buffer has input capacitance 1.2pF so it is ok for my transmitter , but I'm not sure if your buffer can drive good signal (LVDS 2Gbps data, 1GHz clock) to my FPGA.

could you please help me ?

thanks

Sergey

9 months ago

0 David (ASIC) Liu 9 months ago

TI__Guru*** 149805 points

Sergey

Any chance you can use the DS25BR100 EVM and test it out, https://www.ti.com/tool/DS25BR100EVK?

The DS25BR100 is a 3.125G LVDS buffer, so I do not see an issue with it driving a 2G LVDS data. We also have test channel data in its datasheet showing its driving capability.

Thanks
David

0 Sergey Kolen 9 months ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,

your buffer is the same like transmitter, so why your buffer output (transmitter) hasn’t depended on the C input of the load ?

my PHY LVDS (transmitter) promise me 2Gbps for max 2pF of input load, this reason why I put your buffer because I put capacitance of your buffer <2pF, but what is the output rate of your buffer depends on the input capacitance of the load?

0 David (ASIC) Liu 9 months ago in reply to Sergey Kolen

TI__Guru*** 149805 points

Hi,

We have not characterized DS25BR100 with different loading capacitance, and I would recommend you use the DS25BR100 IBIS model to simulate the different loading condition or an EVM for actual physical measurement. The IBIS model is available at this link, https://www.ti.com/product/DS25BR100#design-development.

Thanks

David

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DS25BR100 / DS25BR101 input capacitance