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DS90UB962-Q1: Green screen problem

Part Number: DS90UB962-Q1

Hi team,

My customer has met a green screen problem when using four 933 pairing with 962.

They send us the reg dump of normal status and abnormal status.

I see there is a difference in 0x35, so I doubt that there is something wrong with their camera. Thus I asked them to change other cameras to check if the problem follows camera. The result is that the problem follows 962.

Then I found the configuration of frame synchronization is not right, then I asked them to change. It works but not totally works: Before changes, the problem exists until power-down and power-up. After changes, the problem disappears itself in a few seconds. So it seems like there is still something wrong in the register setting. Can you have a check on it?  I give the reg dump after changes below.

Then I checked their register configuration, I don't see any fault in their config. Pls have a check.

Then they told me they have another project, which uses the same schematic as this one. The only difference is that they use 26MHz crystal in this project, while they use 25MHz crystal in another project. The 25MHz crystal suits well with the system, but the 26MHz crystal has green screen problem.

abnormal reg dump.log
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 60 00 1e 40 d0 01 00 fe 1c 10 7a 7a 0f 09 00 ff    `.?@??.???zz??..
10: 00 00 00 00 00 00 00 00 01 06 83 06 83 00 04 02    ........?????.??
20: 00 3c 04 00 00 00 00 00 00 00 00 00 00 00 00 00    .<?.............
30: 00 00 01 01 00 00 00 0f 00 00 00 00 00 00 00 00    ..??...?........
40: 00 a9 71 01 00 00 20 00 00 00 00 12 38 c3 55 36    .?q?.. ....?8?U6
50: ff 00 00 00 00 00 00 00 58 00 00 b0 b6 00 00 00    ........X..??...
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 8a 88    .............???
70: 1e ec e4 03 c0 0a 00 c5 00 01 00 00 c0 00 00 00    ??????.?.?..?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 08 00 07 58 ff ff ff ff 00 00 00 00 00 00 00 00    ?.?X............
a0: 00 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00    .....?..........
b0: 1c 3a 15 08 25 00 18 00 8f 3f 83 74 80 00 00 00    ?:??%.?.???t?...
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 43 94 02 60 f2 00 02 00 00 00 10 00 00 00 00    .C??`?.?...?....
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00    _UB960..........

normal reg dump.log
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 60 00 1e 40 d0 01 00 fe 1c 10 7a 7a 0f 09 00 ff    `.?@??.???zz??..
10: 00 00 00 00 00 00 00 00 01 06 83 06 83 00 04 02    ........?????.??
20: 00 3c 05 00 00 00 00 00 00 00 00 00 00 00 00 00    .<?.............
30: 00 00 01 01 00 03 00 0f 00 00 00 00 00 00 00 00    ..??.?.?........
40: 00 a9 71 01 00 00 20 00 00 00 00 12 38 c3 55 2e    .?q?.. ....?8?U.
50: 9b 00 00 00 00 00 00 00 58 00 00 b0 b6 00 00 00    ?.......X..??...
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 7f 8a 88    .............???
70: 1e ec e4 03 c0 0a 00 c5 00 01 00 00 c0 00 00 00    ??????.?.?..?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 13 58 12 e4 ff ff ff ff 00 00 00 00 00 00 00 00    ?X??............
a0: 00 00 00 00 00 1d 00 00 00 00 00 00 00 00 00 00    .....?..........
b0: 1c 3a 15 08 25 00 18 00 8f 3f 83 74 80 00 00 00    ?:??%.?.???t?...
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 43 94 02 60 f2 00 02 00 00 00 00 00 00 00 00    .C??`?.?........
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 36 30 00 00 00 00 00 00 00 00 00 00    _UB960..........

MB.13_AVM_DS90UB962Q1.pdf

962 config.txt
addr 0x30, reg 01 val 01
addr 0x30, reg 19 val 06
addr 0x30, reg 1a val c5
addr 0x30, reg 1b val 06
addr 0x30, reg 1c val c5
addr 0x30, reg 1f val 02
addr 0x30, reg 20 val f0
addr 0x30, reg 4c val 01
addr 0x30, reg 58 val 58
addr 0x30, reg 5c val b0
addr 0x30, reg 6d val 7f
addr 0x30, reg 6e val 8a
addr 0x30, reg 70 val 1e
addr 0x30, reg 72 val e4
addr 0x30, reg 7c val c0
addr 0x30, reg 4c val 02
addr 0x30, reg 58 val 58
addr 0x30, reg 5c val b2
addr 0x30, reg 6d val 7f
addr 0x30, reg 6e val 8a
addr 0x30, reg 70 val 1e
addr 0x30, reg 72 val e4
addr 0x30, reg 7c val c0
addr 0x30, reg 4c val 04
addr 0x30, reg 58 val 58
addr 0x30, reg 5c val b4
addr 0x30, reg 6d val 7f
addr 0x30, reg 6e val 8a
addr 0x30, reg 70 val 1e
addr 0x30, reg 72 val e4
addr 0x30, reg 7c val c0
addr 0x30, reg 4c val 08
addr 0x30, reg 58 val 58
addr 0x30, reg 5c val b6
addr 0x30, reg 6d val 7f
addr 0x30, reg 6e val 8a
addr 0x30, reg 70 val 1e
addr 0x30, reg 72 val e4
addr 0x30, reg 7c val c0
addr 0x30, reg 18 val 01
addr 0x30, reg 21 val 3c
addr 0x30, reg 32 val 01
addr 0x30, reg 33 val 01
addr 0x30, reg b9 val 3f
addr 0x30, reg 4c val 01
addr 0x30, reg 4c val 12
addr 0x30, reg 4c val 24
addr 0x30, reg 4c val 38
addr 0x30, reg 20 val 00

Questions:

1. Is there any fault on their register configuration?

2. Is there any fault on their schematic?

3. What should we do and test in next step?

Since this project is in mass production status, my customer is under great pressure. Pls give me the answer asap. Thanks for your support.

Regards,

Peter

  • Let me jump in to clarify one of the key questions from customer:

    What changes need to make if customer change the REFCLK from 25MHz to 26MHz?

    I think customer just need to change the 0x19 to 0x1C to match the 25fps internal generated frame sync, no other software configuration are needed if 25MHz REFCLK already work good. --pls refer to the configuration code, i don't see any other concern. 

  • Hi Peter, 

    First, can you please provide information on the customer for this issue? 

    Tier 1: 

    OEM: 

    The DS90UB962 is in non-synchronous mode with a back channel rate of 2.5Mbps. In both register dumps there is a line length change, line count change, and buffer error reported in register 0x4E. A buffer error indicates that the sum of the bandwidth going into the 962 is exceeding the output bandwidth.

    • 933 Reference Clock: ? 
    • Imager horizontal active pixels: ?  
    • Imager vertical total lines: ? 
    • Frame rate (Hz): ?
    • Data bits per pixel: ?
    • Forwarding Mode: Synchronous forwarding with Line Concatenation
    • CSI-2 TX lane rate: 800Mbps/lane
    • # of CSI-2 lanes: 4 lanes 
    • CSI-2 clock type: Discontinuous clock 

    From the current configuration, the link rate will be dependent on the 933 reference clock. Would you be able to provide a register dump for the 933 as well? 

    When other cameras were tested, were these 933 cameras with the same design? Did the issue not occur when the camera was changed? 

    Best,

    Zoe

  • Hi Zoe,

    Tier 1:  BICV

    OEM: FAW

    933 Reference Clock: 30.72M
    Imager horizontal active pixels: 1280
    Imager vertical total lines: 960
    Frame rate (Hz): 25

    They cannot dump 933 register because of some technical problem.

    All the cameras are the same. They change the camera and find the problem follows 962.

    They use 25M crystal before, everything is ok. And they use 26M crystal now, they see the green screen.

    Can you tell us what register and configuration should be changed when they change the frequency of the crystal?

    I think we just need to change 0x19-0x1C. No other things need to be changed. Is it right?

    Regards,

    Peter

  • Hi Peter, 

    When using the 26MHz oscillator, the output speed of the CSI-2 transmitter will be 832Mbps instead of 800Mbps. This would be the primary change for the system. Is this currently being accommodated for? 

    Best,

    Zoe

  • Hi Zoe,

    I am not sure if I speak in an unclear way. Now my customer just change the frequency of oscillator from 25MHz to 26MHz, then the problem occurs. They just want to know if they configure the register in a right way.

    Change:

    register 0x19: from 0x06 to 0x06

    register 0x1a: from 0x83 to 0xC5

    register 0x1b: from 0x06 to 0x06

    register 0x1c: from 0x83 to 0xC5

    1. If the answer is YES, we can tell our customer that our setting is right, then they can see if the problem is in oscillator and 933.

    2. If the answer is NO, please tell me what other register and HW should be changed.

    Regards,

    Peter

  • Hi Peter, 

    I see. Yes, this is correct. The frame sync parameters would change due to the increased reference clock.The frame sync signal is derived from the back channel clock rate.

    As a reminder, the REFCLK will change the back channel rate, CSI-2 output, and I2C timers. 

    Best,

    Zoe

  • Hi Zoe,

    Got it, I will tell the customer about this. 

    As a reminder, the REFCLK will change the back channel rate, CSI-2 output, and I2C timers.

    For the change of BC rate, CSI output, should they change any other thing in the system(933, camera, SOC)? 

    Regards,

    Peter

  • Hi Peter, 

    The SOC must be able to accept 832Mbps per lane on the CSI-2 input. Register 0xA and 0xB will change the SCL High and Low time for I2C. 

    Best,

    Zoe