TLK10232: Value of HS SERDES multiplier setting

Panayotis Tziaros

Part Number: TLK10232

Hello,

We have used TLK10232 dual phy component for a XAUI to SFP/SFP+ application.

I have a question regarding the value of HS SERDES multiplier setting (Reg 0x1e.0x0002.[3:0])

We operate the chip at REFCLK frequency set to 156.25MHz.

According to HS PLL Multiplier Control Table when this frequency is used the PLL multiplier factor should be 16.5x (value 1100b) but we erroneously use the value 1101b (default) that corrensponds to 20x.

Trying both values seems to have no real impact to phy operation.

How this can be explained?

Note that Auto-Negotiation & Link Training are disabled.

Thanks on advance,

Panayotis

6 months ago

Drew Miller1 6 months ago

TI__Mastermind 19741 points

Hi Panayotis,

I'm looking into this and expect to get back to you with more details mid-week.

Thanks,

Drew

Drew Miller1 6 months ago in reply to Drew Miller1

TI__Mastermind 19741 points

Hi Panayotis,

Apologies for the delay on this.

I believe the reason for your observations is that Reg 0x1E.0x001D[13]=0. If this is the case, then the HS_PLL_MULT setting is not used.

Thanks,

Drew

Panayotis Tziaros 6 months ago in reply to Drew Miller1

Prodigy 40 points

Hi Drew,

I checked the register you mention and this is the case.

Thanks for your time.

Regards,

Panayotis

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TLK10232: Value of HS SERDES multiplier setting