TCA9803: IBIS Model

Hi again,

I can see that the SCL/SDA_A is much stronger and faster than the B-side, I wonder if you have similar I2C level translator product (both side 3V3) but with weaker A-side? Thanks.

Hi Li,

The expert supporting this case is currently out- I will try my best to fill in for the time being. 

By "weaker" did you mean a higher VOL is desired, except on A-side? Since VCCA = VCCB, are you able to swap A and B side to match the desired VOL? 

You can also see the TCA9517/TCA9617 that has a heightened VOL on B-side and configure it on your A side instead.

Regards,

Jack 

Thanks for the reply. For this application, a buffer is good enough since we do have the same 3V3 on both sides, just belong to different power domain. 

I'm talking about the logic low signal. With the SDAA pulling low, the equivlent output impedance is quite small and the fall edge is pretty fast which causes some issues with our super long I2C channel. I wonder if any similar device with much weaker driver so longer falling time. Thanks.

We currently see the issue within simulation while using IBIS model. Our application has a very long I2C channel, with the total electrical length of around 11ns, therefore comparing to the typ 9ns falling time of this device, the channel is not lumped length any more which would create an overshoot at the receiver end. In simulation, we need to add a Rserial to dump that. If to add a Cshunt, it could also work but with a large cap value, and considering the other devices on the line, that will make the risetime too slow to meet the standard requirement.

I'm thinking if there is a footprint compatible device as TCA980x but with weaker driver with falling time much longer like 40ns or so, so that our long channel could be treated as lumped length, then we could be benefit from it. 

Thanks for the recommendation. The proposed part looks promising. However, there are some additional issue that I want to double check regarding the IBIS model. It's very simple setup as shown below, and the TRL is 1ns, Pull up Res is 2k, and Cshunt is set to be open, all drivers are set with 3V3 for TCA9517, and 3V6 for 9802. 

The following is the result plot. The questions are:

1. VOL level for 9802_B is very high

2. The ringing shown at the rise edge for 9517_A. 

Could you pls double check the IBIS model and confirm if it would be the true phenomenon or if it is simulation only.

Thanks a lot.

Of course, that I have missed in my previous setup. However, in the simulation, even if I removed everything at the output, so it is purely TCA9802_B driver, the low level lowered a bit but is still close to 2V. Is there anything else that I missed in the setup?

BR
Li

Hi Li,

I am wondering if it is a model concern. Can you try setting the VCC of the TCA9802 to 3.6V instead of 3.3V? 

Regards,

Tyler

Hi Tyler,

I also a bit suspect if it is the model. Now I've set it so that it has only the SDAB driver with no load, as shown below. I've set all 3 different voltage level options, and for each driver, it is powered internally and output only 1010. 

This is how the output curve looks like below, with VOL 0.38-2.07V. While in the datasheeet, it actuallys states typ VOL 0.22V and max 0.26V for TCA9802.

Li,

Yeah this looks like the model is off on the VOLB. Unfortunately our process to update this type of model is normally done by the design team in the past. Given that this is an older model (2017), it would take some time to redo this model and since most of our team is ooo until January 2nd due to holiday, work towards a new model would be further delayed. 

How important is this model for sim? If we decide to proceed with the update of this model, I would need to consult my team to get an idea of how much work this would be. My suspicion is that is could be several weeks from today to produce an updated model. 

Regards,

Tyler

Hi Tyler,

Thanks for the confirmation. I want to bring up another thing about the TCA9517 sideA model. Simple setup with 2k Pull Up resistor. Output 1010. Same setup for sideA and sideB model.

This is the output plot. As pointed, the rise edge shows ringing effect which should not exist for open drain buffer. Could you also check this? Thanks.

We want to finalize our design late January. It would be very helpful if we could get the updated model before that.

Again, thanks for quick response!

BR

Li

Ok, thanks for the inforamtion, so we know we should not wait for the simulation to qualify the device. We have been using this device before, so in normal user case it should be fine. However, I'd appreciate it very much if I could get updated once there are new version of the models. 
Thanks again for all the discussion!