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TLK10022: TLK10022/TLK10081 Aggregator BER testing

dean ingram
Prodigy 30 points
Part Number: TLK10022

We would like to setup a BER test using loop backs connecting HS TX transmitting PRBS pattern to HS RX inputs and monitoring for bit errors detected.

Is there a way to understand what the EVM GUI is doing so we can replicate it in our system?

Or

Is there a way to understand what register settings are required for this test setup?

Thanks

  • 0
    TI__Genius 16240 points

    Hi,

    Register 0x0B HS_TP_CONTROL can be used to enable/disable the HS test pattern generator and verifier, as well as select a test pattern. Once the HS test pattern verifier is enabled, register 0x0F bit 15 HS_TP_STATUS will tell you if alignment has been achieved. Once alignment is reached, bit errors can be read in register 0x10 HS_ERROR_COUNTER.

    Hope this helps. Please let me know if you have any additional questions.

    Best,

    Lucas