• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 31 subscribers
  • Views 876 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLK10022 Link Aggregator and FPGA

Jan-Philip
Prodigy 20 points
Other Parts Discussed in Thread: TLK10022

Hello!

Normally one would use two TLK10022 to combine and decombine some high speed signals in order to reduce the number of lines required. But we would like to use just one TLK10022 to combine four digital signals of ADCs. The combined signal should then be routed to one Transceiver of the Xilinx FPGA Board VC7203 where it shall be decombined again.

Does anybody know if this approach is possible, or do we might get into trouble because of the protocol overhead and/or some algorithms which the data undergoes before in the TLK10022?

Thank you so much and best regards

Jan-Philip

  • 0
    TI__Genius 16150 points

    Hi Jan,

    It "could be work", although, the ideal application is connect 2 TLK10022 for:

    TLK10022[4x0.25~2.5Gbps ==> 1x1~10Gbps] ==> VC7203 ==> 4x0.25~2.5Gbps

    User must be careful, the FPGA´s transceiver needs to have a similar structure as TLK device, as you know TLK10022 consists of 2 SERDES blocks (LS & HS). The core logic blocks that lies between the low speed and high speed SerDes blocks carry out all the logic functions such as byte alignment, encoding/decoding, lane marking and scrambling.

    Hence, I would not suggest use just one TLK10022 for this application, to avoid issues regarding the protocols, behavior, sync, etc.

    Best Regards!

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team