TFP401A: Conditions where HSYNC is not output

Hello,

 Are you able to see the output ODCK clock and DE signal? What input format mode are you using? 

Please let me know how you are setting the pins as well.

Thanks,

Zach

Zach-san,
Thank you for your answer.

We asked our customers to compare the input signals from the TFP401 and TFP401A camera modules. The input signal standard is YUV422 and the pixel rate is 74.6MHz.
Attached is the pin layout of TFP401A.
TFP401A pin layout.pptx

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

Doing a schematic review will take 1-2 business days. While I work on that could you send waveforms of the input and output signals?

Hi, Support Team.

I got feedback from customers.

SEB9692 board TFP401EVM We measured the DE and CLK signals output from the board. The waveforms output by the customer's evaluation board, TFP401A, and TFP401EVM board are the same.
There is a period in which both DE signals are low for a shorter period than usual, and it seems that Hsync is not being output properly at that time.
By the way, the minimum OFF time of DE is Tpixcel in the data sheet, which is about 13.5ns min compared to CAMpixel,
which seems to have more margin for OFF time,but I wonder if my interpretation is different.

TFP401 DE_Hsync_Vsync.pptx

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

Do you see the same issue when using the TFP401? Have your tried swapping the devices to see if the jitter cleaning was the issue?

Additionally, I'm so sorry that I didn't get to the schematic review ill have it ready for you by end of day today.

Best,

Vishesh Pithadiya

Here is the schematic review.

TFP410_Schematic_Review_Hiroaki(2_15_24).pdf

Additionally, who is the OEM/ ODM for this project, and what is the project name?

Hello Vishesh-san,
Thank you for your support.

We received feedback from our customers.
I can't give you too many details, but it's a screen switching device for medical institutions.

H_sync is not output for both TFP401/TFP401A.
Furthermore, TPF401A does not output CLK.

In the initial settings, customers do not read EDID and output at a fixed resolution.
When using the resolution 1080p 29.97Hz, the output is in the CEA VIC34 format.

The customer would like to know if the CEA VIC34 format is supported.

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

Looking into this now. 

Additionally, why are you pulling up odck?

If the TFP401A does not output a clock this means that the device is no receiving a clock.

From the HSYNC, VSYNC, and DE waveforms it seem that the TFP401A/ TFP401 isn't encoding the input data correctly. In order for the TFP401/A to output the DE signal, blanking must be correctly decoded on 2 of the 3 input channels (DE is encoded in each channel).

Does this happen on one board or multiple boards?

Can you probe the TFP401A input and see if they see a clock? 

Can you look at the input signal with a diff. probe?

Also are there any ESD or other components on the input high-speed signals?

Is the PD# pin is not toggling or noisy as well?

Hello Vishesh-san,
Thank you for your advice.

I told the customer to check. I would also remove the ODCK pull-up resistor and have them check it.
We'll let you know if we receive feedback from our customers.

Best Regards,
Hiroaki Yuyama

Prefect, let me know if this changes/ resolves the issue.

Hello Vishesh-san,
Thank you for your support.

We received feedback from our customers.
Customer comments and waveforms have been updated from page 4 of the PPT File.

CLK is output normally for both TFP401 and TFP401A.
There is no difference when comparing the CLK waveform with the board on which the image is displayed using a different IC on the prototype board.
Therefore, I think there is no problem with the input signal.
Currently, the signals that are not encoded correctly are Hsync and DE signals. Currently, CLK and V_SYNC are output normally,
so the input of CLK and V_SYNK is also normal.
It seems that DE is output normally, but is there a case where DE is not output correctly unless H_SYNK is also decoded correctly?

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

This issue can also be seen in the EVMS which are implemented correctly, meaning that this is very likely an input signal integrity problem.

Additionally, it seems that the clock speed is correct at 74.18MHz. This means that HSYNC should be 33.72kHz, and VSYNC should be at 30Hz. In your waveforms it seems that HSYNC is correct:

Let me know if I am misinterpreting the image. Its very difficult to see the waveforms on a black background. If possible can you send them on a white background?

Are you able to use a protocol analyzer to verify the TMDS signal going in?

Additionally do you have information about the jitter on the inputs. I will try to recreate this issue in the lab with our EVM board.

Hello Vishesh-san,
Thank you for your kind support.

A customer sent us an oscilloscope waveform with a white background.
Also, even if I removed the ODCK pull-up resistor, there was no change in the waveform.

Customer comments and waveforms have been updated from page 8 of the PPT File.
TFP401 DE_Hsync_Vsync_03.pptx
Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

I'm still in the process of getting the equipment I need to try to replicate the issue. 

Vishesh Pithadiya said:

Can you look at the input signal with a diff. probe?

Also are there any ESD or other components on the input high-speed signals?

Is the PD# pin is not toggling or noisy as well?

In the meanwhile can yo have a look at the following questions?

Best,

Vishesh Pithadiya

Hello Vishesh-san,

I have received feedback from customers.

They measured the HDMI input signals (CLK, data0, data1, data2) using a differential probe.
The Customer waveforms have been updated from page 16 of the PPT File.
7446.TFP401 DE_Hsync_Vsync_03.pptx

We also measured the PD pin while inputting a video signal,and the customer says that no particular noise was generated.

I hope this information helps you reproduce the problem.

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

I finally have all the equipment I need, so I will try to replicate this issue in lab. 

Doe the HSYNC skip affect the output video RGB video? Also are you able to change the video format from YUV 4:2:2 to RGB?

Also is the PD pin noisy in any way?

Do you see this HSYNC skip on multiple boards, or just this one?

Sorry for the delay in getting the testing done in lab.

I just got back from a week long business trip.

Hello Vishesh-san,

Thank you for your reply.

We have passed your question back to the customer.
We also asked about the frequency and conditions under which Hsync is missing.

I hope you can replicate the issue.

Best Regards,
Hiroaki Yuyama

Hey Hiroaki,

I will try to have some data ready by the end of today

Hello Vishesh-san,

Thank you for the lab testing in your customer's condition.

I asked the customer for detailed conditions under which H_SYNC would be missing.
When H_SYNC is missing, have the customer check again to see if there is anything nearby that could be a trigger.

Thanks and Best Regards,
Hiroaki Yuyama

Hello Vishesh-san,
Thank you for your support.

Thank you for testing us in your lab. Please let us know the video resolution you used so we can see the difference with the customer's operating environment. In the latest communication from a customer, the correct output format for the video format was RGB, not YUV422. If possible, could you please check it again in RGB format?

We received feedback from our customers. Hsync skips occur frequently and occur on every board.
The skip interval is about 29.97Hz. The camera module used by the customer is EIZO's SSZ-9700,and the same problem occurs even in RGB format.
Please let me know if there are any problems when using this module with the TPF401 series.
https://www.eizoglobal.com/products/duravision/ssz-9700/

Best Regards,
Hiroaki Yuyama

Hey Hiroaki-san,

The video resolution for the test was 1920x1080 @29.98 Hz.

The video format was RGB with no audio.

Hello Vishesh-san,
Thank you for your reply.

We told the customer the video format and video resolution you tested in the lab.
We believe the problem lies with the customer. We will let the customer solve the problem themselves.
Thank you for your tremendous support.

Best Regards,
Hiroaki Yuyama