TCAN4550-Q1: Trouble with TCAN4550-Q1 CAN Controller

Hi Anand,

If you are seeing signals on the CANH and CANL pins that when the TCAN4550 transmits a message, then perhaps there is an issue with the bit timing configuration matching those of the CANoe and PCAN.  What do the waveforms for a full CAN message frame look like?  Are the messages getting acknowledged, or are there error flags being generated by the CANoe and PCAN modules?  Can you capture and provide the waveforms for a full CAN message?

Can you confirm what the Nominal and Data bit timing settings are for both the TCAN4550 and CANoe and PCAN modules?

Regards,

Jonathan

Hi Jonathan, 

 Thanks for your reply, I've tried matching the sample-points, phase segs values of the target to the deafault values of PCAN tool, And I was gettting BUS HEAVY and then BUSOFF error on the trace window while I sent messeges from the target device and sometimes messeges are not being acknowledged, Scope also is reading Error Frames/ unexpected Data on the lines, Also I've measured the resistance accross the test points of the CANH and CANL wires and I'm getting value 124 Ohms, could this be also one of the reason, I've attached the images below.

Hi Anand,

I don't have direct experience with the PCAN analyzer tool you are using, but through some research I have found that other's have said the BUS HEAVY fault is either due to incorrect or missing bus termination, or incorrect bit timing settings, and the clock source may not be adequate and they referenced an 8MHz clock frequency.

A properly terminated CAN bus has two sets of 120 ohm termination resistors with one set placed at each end of the bus.  They are in parallel so the bus impedance should be approximately 60 ohms.  Because you are measuring 124 ohms, I suspect you are missing a set of termination resistors which could be leading to the errors.

I also see in your screenshot of the PCAN configuration that it shows a clock frequency of 8Mhz.  Typical clock frequencies used in CAN are higher such as 20MHz, 40MHz, 80MHz, etc.  Do you have a faster clock option?

If you can provide me a schematic diagram of your setup and TCAN4550 circuit, I can review that for any possible errors or improvements.

If you can provide me a list of the final register values you are using in your TCAN4550 configuration, I can also review that for any possible issues.

Regards,

Jonathan

Hi Jonathan,

The TCAN4x5x driver code used in our project is sourced directly from the official Linux kernel repository hosted on GitHub at [https://github.com/torvalds/linux/tree/master/drivers/net/can/m_can. I have not made any modifications to the driver code itself. As per my understanding the specific register values are typically determined by the initialization routines, interrupt handlers, and configuration settings applied during runtime ,

I have attached a schematic diagram illustrating the setup of the TCAN4550 circuit within my system.

Thank you for your support.

Regards,

Anand Kulkarni

Hi Anand,

I understand you are using the Linux community's driver code and that it will set many of the configuration registers during runtime.  This unfortunately doesn't not provide me with any information to help you debug your issues because I don't know how the device is configured, and I don't know what status and interrupt bits may be getting set that could indicate the issue.

I believe there are functions in the driver for reading the TCAN4550 registers.  Is it not possible to simply read back all of the device register to some form or log file or to a UART terminal at the end of the configuration sequence so that we can verify what settings the driver code is using and make sure the bit timing settings match the PCAN settings?

I see one issue with the schematic but I'm not sure it is causing any troubles at this time.  The series resistor between the OSC2 pin and the crystal (R384) should be located between the OSC1 pin and the crystal.  The OSC1 pin is the "output" of TCAN4550's current transconductance amplifier feeding current to the crystal, and the OSC2 pin is the "input".  This is common misunderstanding because when a single-ended clock is used instead of a crystal, the OSC1 pin becomes the "input" pin for the single-ended clock and the OSC2 pin is grounded.

You can reference the TCAN455x Clock Optimization and Design Guidelines application note for more information. (Link)

Regards,

Jonathan

Hello Jonathan,
  As I am relatively new to this task, I'm uncertain if this approach is correct, I have attempted to read the register values through SPI using the following code :

#include <stdio.h>
#include <stdint.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <linux/spi/spidev.h>

static const char *device = "/dev/spidev2.0";
static uint8_t mode = SPI_MODE_0;
static uint8_t bits = 8;
static uint32_t speed = 1000000; // 1 MHz
static uint16_t delay = 0;

#define REG_MCAN_CREL    0x1000
#define REG_MCAN_ENDN    0x1004
#define REG_MCAN_CUST    0x1008
#define REG_MCAN_DBTP    0x100C
#define REG_MCAN_TEST    0x1010
#define REG_MCAN_RWD     0x1014
#define REG_MCAN_CCCR    0x1018
#define REG_MCAN_NBTP    0x101C
#define REG_MCAN_TSCC    0x1020
#define REG_MCAN_TSCV    0x1024
#define REG_MCAN_TOCC    0x1028
#define REG_MCAN_TOCV    0x102C
#define REG_MCAN_ECR     0x1040
#define REG_MCAN_PSR     0x1044
#define REG_MCAN_TDCR    0x1048
#define REG_MCAN_IR      0x1050
#define REG_MCAN_IE      0x1054
#define REG_MCAN_ILS     0x1058
#define REG_MCAN_ILE     0x105C
#define REG_MCAN_GFC     0x1080
#define REG_MCAN_SIDFC   0x1084
#define REG_MCAN_XIDFC   0x1088
#define REG_MCAN_XIDAM   0x1090
#define REG_MCAN_HPMS    0x1094
#define REG_MCAN_NDAT1   0x1098
#define REG_MCAN_NDAT2   0x109C
#define REG_MCAN_RXF0C   0x10A0
#define REG_MCAN_RXF0S   0x10A4
#define REG_MCAN_RXF0A   0x10A8
#define REG_MCAN_RXBC    0x10AC
#define REG_MCAN_RXF1C   0x10B0
#define REG_MCAN_RXF1S   0x10B4
#define REG_MCAN_RXF1A   0x10B8
#define REG_MCAN_RXESC   0x10BC
#define REG_MCAN_TXBC    0x10C0
#define REG_MCAN_TXFQS   0x10C4
#define REG_MCAN_TXESC   0x10C8
#define REG_MCAN_TXBRP   0x10CC
#define REG_MCAN_TXBAR   0x10D0
#define REG_MCAN_TXBCR   0x10D4
#define REG_MCAN_TXBTO   0x10D8
#define REG_MCAN_TXBCF   0x10DC
#define REG_MCAN_TXBTIE  0x10E0
#define REG_MCAN_TXBCIE  0x10E4
#define REG_MCAN_TXEFC   0x10F0
#define REG_MCAN_TXEFS   0x10F4
#define REG_MCAN_TXEFA   0x10F8

uint32_t spi_read_register(int fd, uint16_t address) {
    uint8_t tx_buffer[4], rx_buffer[4];
    uint32_t value;

    tx_buffer[0] = 0x80 | ((address >> 8) & 0xFF);
    tx_buffer[1] = address & 0xFF;
    tx_buffer[2] = 0x00;
    tx_buffer[3] = 0x00;

    struct spi_ioc_transfer tr = {
        .tx_buf = (unsigned long)tx_buffer,
        .rx_buf = (unsigned long)rx_buffer,
        .len = 4,
        .delay_usecs = delay,
        .speed_hz = speed,
        .bits_per_word = bits,
    };

    if (ioctl(fd, SPI_IOC_MESSAGE(1), &tr) < 1) {
        perror("SPI_IOC_MESSAGE");
        return -1;
    }

    value = (rx_buffer[3] << 24) | (rx_buffer[2] << 16) | (rx_buffer[1] << 8) | rx_buffer[0];
    return value;
}
int main() {
    int fd;

    if ((fd = open(device, O_RDWR)) < 0) {
        perror("open");
        return 1;
    }

    if (ioctl(fd, SPI_IOC_WR_MODE, &mode) < 0) {
        perror("ioctl (SPI_IOC_WR_MODE)");
        return 1;
    }

    if (ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits) < 0) {
        perror("ioctl (SPI_IOC_WR_BITS_PER_WORD)");
        return 1;
    }

    if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) < 0) {
        perror("ioctl (SPI_IOC_WR_MAX_SPEED_HZ)");
        return 1;
    }

    uint32_t cccr_value = spi_read_register(fd, REG_MCAN_CCCR);
    uint32_t crel_value = spi_read_register(fd, REG_MCAN_CREL);
    uint32_t endn_value = spi_read_register(fd, REG_MCAN_ENDN);
    uint32_t cust_value = spi_read_register(fd, REG_MCAN_CUST);
    uint32_t dbtp_value = spi_read_register(fd, REG_MCAN_DBTP);
    uint32_t test_value = spi_read_register(fd, REG_MCAN_TEST);
    uint32_t rwd_value = spi_read_register(fd, REG_MCAN_RWD);
    uint32_t nbtp_value = spi_read_register(fd, REG_MCAN_NBTP);
    uint32_t tscc_value = spi_read_register(fd, REG_MCAN_TSCC);
    uint32_t tscv_value = spi_read_register(fd, REG_MCAN_TSCV);
    uint32_t tocc_value = spi_read_register(fd, REG_MCAN_TOCC);
    uint32_t tocv_value = spi_read_register(fd, REG_MCAN_TOCV);
    uint32_t ecr_value = spi_read_register(fd, REG_MCAN_ECR);
    uint32_t psr_value = spi_read_register(fd, REG_MCAN_PSR);
    uint32_t tdcr_value = spi_read_register(fd, REG_MCAN_TDCR);
    uint32_t ir_value = spi_read_register(fd, REG_MCAN_IR);
    uint32_t ie_value = spi_read_register(fd, REG_MCAN_IE);
    uint32_t ils_value = spi_read_register(fd, REG_MCAN_ILS);
    uint32_t ile_value = spi_read_register(fd, REG_MCAN_ILE);
    uint32_t gfc_value = spi_read_register(fd, REG_MCAN_GFC);
    uint32_t sidfc_value = spi_read_register(fd, REG_MCAN_SIDFC);
    uint32_t xidfc_value = spi_read_register(fd, REG_MCAN_XIDFC);
    uint32_t xidam_value = spi_read_register(fd, REG_MCAN_XIDAM);
    uint32_t hpms_value = spi_read_register(fd, REG_MCAN_HPMS);
    uint32_t ndat1_value = spi_read_register(fd, REG_MCAN_NDAT1);
    uint32_t ndat2_value = spi_read_register(fd, REG_MCAN_NDAT2);
    uint32_t rxf0c_value = spi_read_register(fd, REG_MCAN_RXF0C);
    uint32_t rxf0s_value = spi_read_register(fd, REG_MCAN_RXF0S);
    uint32_t rxf0a_value = spi_read_register(fd, REG_MCAN_RXF0A);
    uint32_t rxbc_value = spi_read_register(fd, REG_MCAN_RXBC);
    uint32_t rxf1c_value = spi_read_register(fd, REG_MCAN_RXF1C);
    uint32_t rxf1s_value = spi_read_register(fd, REG_MCAN_RXF1S);
    uint32_t rxf1a_value = spi_read_register(fd, REG_MCAN_RXF1A);
    uint32_t rxesc_value = spi_read_register(fd, REG_MCAN_RXESC);
    uint32_t txfqs_value = spi_read_register(fd, REG_MCAN_TXFQS);
    uint32_t txesc_value = spi_read_register(fd, REG_MCAN_TXESC);
    uint32_t txbrp_value = spi_read_register(fd, REG_MCAN_TXBRP);
    uint32_t txbar_value = spi_read_register(fd, REG_MCAN_TXBAR);
    uint32_t txocr_value = spi_read_register(fd, REG_MCAN_TXBCR);
    uint32_t txbto_value = spi_read_register(fd, REG_MCAN_TXBTO);
    uint32_t txbc_value = spi_read_register(fd, REG_MCAN_TXBCF);
    uint32_t txbtie_value = spi_read_register(fd, REG_MCAN_TXBTIE);
    uint32_t txbcie_value = spi_read_register(fd, REG_MCAN_TXBCIE);
    uint32_t txefc_value = spi_read_register(fd, REG_MCAN_TXEFC);
    uint32_t txefs_value = spi_read_register(fd, REG_MCAN_TXEFS);
    uint32_t txefa_value = spi_read_register(fd, REG_MCAN_TXEFA);

    close(fd);

    printf("Value from REG_MCAN_CCCR register (little-endian): %08X\n", cccr_value);
    printf("Value from REG_MCAN_CREL register (little-endian): %08X\n", crel_value);
    printf("Value from REG_MCAN_ENDN register (little-endian): %08X\n", endn_value);
    printf("Value from REG_MCAN_CUST register (little-endian): %08X\n", cust_value);
    printf("Value from REG_MCAN_DBTP register (little-endian): %08X\n", dbtp_value);
    printf("Value from REG_MCAN_TEST register (little-endian): %08X\n", test_value);
    printf("Value from REG_MCAN_RWD register (little-endian): %08X\n", rwd_value);
    printf("Value from REG_MCAN_NBTP register (little-endian): %08X\n", nbtp_value);
    printf("Value from REG_MCAN_TSCC register (little-endian): %08X\n", tscc_value);
    printf("Value from REG_MCAN_TSCV register (little-endian): %08X\n", tscv_value);
    printf("Value from REG_MCAN_TOCC register (little-endian): %08X\n", tocc_value);
    printf("Value from REG_MCAN_TOCV register (little-endian): %08X\n", tocv_value);
    printf("Value from REG_MCAN_ECR register (little-endian): %08X\n", ecr_value);
    printf("Value from REG_MCAN_PSR register (little-endian): %08X\n", psr_value);
    printf("Value from REG_MCAN_TDCR register (little-endian): %08X\n", tdcr_value);
    printf("Value from REG_MCAN_IR register (little-endian): %08X\n", ir_value);
    printf("Value from REG_MCAN_IE register (little-endian): %08X\n", ie_value);
    printf("Value from REG_MCAN_ILS register (little-endian): %08X\n", ils_value);
    printf("Value from REG_MCAN_ILE register (little-endian): %08X\n", ile_value);
    printf("Value from REG_MCAN_GFC register (little-endian): %08X\n", gfc_value);
    printf("Value from REG_MCAN_SIDFC register (little-endian): %08X\n", sidfc_value);
    printf("Value from REG_MCAN_XIDFC register (little-endian): %08X\n", xidfc_value);
    printf("Value from REG_MCAN_XIDAM register (little-endian): %08X\n", xidam_value);
    printf("Value from REG_MCAN_HPMS register (little-endian): %08X\n", hpms_value);
    printf("Value from REG_MCAN_NDAT1 register (little-endian): %08X\n", ndat1_value);
    printf("Value from REG_MCAN_NDAT2 register (little-endian): %08X\n", ndat2_value);
    printf("Value from REG_MCAN_RXF0C register (little-endian): %08X\n", rxf0c_value);
    printf("Value from REG_MCAN_RXF0S register (little-endian): %08X\n", rxf0s_value);
    printf("Value from REG_MCAN_RXF0A register (little-endian): %08X\n", rxf0a_value);
    printf("Value from REG_MCAN_RXBC register (little-endian): %08X\n", rxbc_value);
    printf("Value from REG_MCAN_RXF1C register (little-endian): %08X\n", rxf1c_value);
    printf("Value from REG_MCAN_RXF1S register (little-endian): %08X\n", rxf1s_value);
    printf("Value from REG_MCAN_RXF1A register (little-endian): %08X\n", rxf1a_value);
    printf("Value from REG_MCAN_RXESC register (little-endian): %08X\n", rxesc_value);
    printf("Value from REG_MCAN_TXBC register (little-endian): %08X\n", txbc_value);
    printf("Value from REG_MCAN_TXFQS register (little-endian): %08X\n", txfqs_value);
    printf("Value from REG_MCAN_TXESC register (little-endian): %08X\n", txesc_value);
    printf("Value from REG_MCAN_TXBRP register (little-endian): %08X\n", txbrp_value);
    printf("Value from REG_MCAN_TXBAR register (little-endian): %08X\n", txbar_value);
    printf("Value from REG_MCAN_TXBCR register (little-endian): %08X\n", txocr_value);
    printf("Value from REG_MCAN_TXBTO register (little-endian): %08X\n", txbto_value);
    printf("Value from REG_MCAN_TXBCF register (little-endian): %08X\n", txbc_value);
    printf("Value from REG_MCAN_TXBTIE register (little-endian): %08X\n", txbtie_value);
    printf("Value from REG_MCAN_TXBCIE register (little-endian): %08X\n", txbcie_value);
    printf("Value from REG_MCAN_TXEFC register (little-endian): %08X\n", txefc_value);
    printf("Value from REG_MCAN_TXEFS register (little-endian): %08X\n", txefs_value);
    printf("Value from REG_MCAN_TXEFA register (little-endian): %08X\n", txefa_value);

    return 0;
}

Below are the outputs I obtained before and after setting up the CAN network interface:

[14:55] Anand S. Kulkarni
root@ambarella-vcam:/usr/bin# testtcan

Value from REG_MCAN_CCCR register (little-endian): 000C4800

Value from REG_MCAN_CREL register (little-endian): 00004866

Value from REG_MCAN_ENDN register (little-endian): 00024866

Value from REG_MCAN_CUST register (little-endian): 00044866

Value from REG_MCAN_DBTP register (little-endian): 00064866

Value from REG_MCAN_TEST register (little-endian): 00084866

Value from REG_MCAN_RWD register (little-endian): 000A4866

Value from REG_MCAN_NBTP register (little-endian): 000E4866

Value from REG_MCAN_TSCC register (little-endian): 00104866

Value from REG_MCAN_TSCV register (little-endian): 00124866

Value from REG_MCAN_TOCC register (little-endian): 00144866

Value from REG_MCAN_TOCV register (little-endian): 00164866

Value from REG_MCAN_ECR register (little-endian): 00204866

Value from REG_MCAN_PSR register (little-endian): 00224866

Value from REG_MCAN_TDCR register (little-endian): 00244866

Value from REG_MCAN_IR register (little-endian): 00284866

Value from REG_MCAN_IE register (little-endian): 00664866

Value from REG_MCAN_ILS register (little-endian): 00664866

Value from REG_MCAN_ILE register (little-endian): 002E6666

Value from REG_MCAN_GFC register (little-endian): 00406666

Value from REG_MCAN_SIDFC register (little-endian): 00424866

Value from REG_MCAN_XIDFC register (little-endian): 00444866

Value from REG_MCAN_XIDAM register (little-endian): 00484866

Value from REG_MCAN_HPMS register (little-endian): 004A4866

Value from REG_MCAN_NDAT1 register (little-endian): 004C4866

Value from REG_MCAN_NDAT2 register (little-endian): 004E4866

Value from REG_MCAN_RXF0C register (little-endian): 00504866

Value from REG_MCAN_RXF0S register (little-endian): 00524866

Value from REG_MCAN_RXF0A register (little-endian): 00544866

Value from REG_MCAN_RXBC register (little-endian): 00564866

Value from REG_MCAN_RXF1C register (little-endian): 00664866

Value from REG_MCAN_RXF1S register (little-endian): 005A6666

Value from REG_MCAN_RXF1A register (little-endian): 005C6666

Value from REG_MCAN_RXESC register (little-endian): 005E6666

Value from REG_MCAN_TXBC register (little-endian): 006E4866

Value from REG_MCAN_TXFQS register (little-endian): 00624866

Value from REG_MCAN_TXESC register (little-endian): 00444866

Value from REG_MCAN_TXBRP register (little-endian): 00664866

Value from REG_MCAN_TXBAR register (little-endian): 00684866

Value from REG_MCAN_TXBCR register (little-endian): 006A4866

Value from REG_MCAN_TXBTO register (little-endian): 006C4866

Value from REG_MCAN_TXBCF register (little-endian): 006E4866

Value from REG_MCAN_TXBTIE register (little-endian): 00704866

Value from REG_MCAN_TXBCIE register (little-endian): 00724866

Value from REG_MCAN_TXEFC register (little-endian): 00786666

Value from REG_MCAN_TXEFS register (little-endian): 007A4866

Value from REG_MCAN_TXEFA register (little-endian): 007C4866

root@ambarella-vcam:/usr/bin# sudo ip link set can0 type can bitrate 500000

root@ambarella-vcam:/usr/bin# sudo ip link set can0 up

root@ambarella-vcam:/usr/bin# testtcan

Value from REG_MCAN_CCCR register (little-endian): 000C4800

Value from REG_MCAN_CREL register (little-endian): 00004866

Value from REG_MCAN_ENDN register (little-endian): 00024866

Value from REG_MCAN_CUST register (little-endian): 00044866

Value from REG_MCAN_DBTP register (little-endian): 00064866

Value from REG_MCAN_TEST register (little-endian): 00084866

Value from REG_MCAN_RWD register (little-endian): 000A4866

Value from REG_MCAN_NBTP register (little-endian): 000E4866

Value from REG_MCAN_TSCC register (little-endian): 00106666

Value from REG_MCAN_TSCV register (little-endian): 00106666

Value from REG_MCAN_TOCC register (little-endian): 00664866

Value from REG_MCAN_TOCV register (little-endian): 00664866

Value from REG_MCAN_ECR register (little-endian): 66204866

Value from REG_MCAN_PSR register (little-endian): 00664866

Value from REG_MCAN_TDCR register (little-endian): 00664866

Value from REG_MCAN_IR register (little-endian): 66284866

Value from REG_MCAN_IE register (little-endian): 00664866

Value from REG_MCAN_ILS register (little-endian): 00664866

Value from REG_MCAN_ILE register (little-endian): 00664866

Value from REG_MCAN_GFC register (little-endian): 00406666

Value from REG_MCAN_SIDFC register (little-endian): 00426666

Value from REG_MCAN_XIDFC register (little-endian): 00444866

Value from REG_MCAN_XIDAM register (little-endian): 00664866

Value from REG_MCAN_HPMS register (little-endian): 664A0866

Value from REG_MCAN_NDAT1 register (little-endian): 004C6666

Value from REG_MCAN_NDAT2 register (little-endian): 00664866

Value from REG_MCAN_RXF0C register (little-endian): 00664866

Value from REG_MCAN_RXF0S register (little-endian): 00664866

Value from REG_MCAN_RXF0A register (little-endian): 00664866

Value from REG_MCAN_RXBC register (little-endian): 00664866

Value from REG_MCAN_RXF1C register (little-endian): 00664866

Value from REG_MCAN_RXF1S register (little-endian): 00664866

Value from REG_MCAN_RXF1A register (little-endian): 00664866

Value from REG_MCAN_RXESC register (little-endian): 005E6666

Value from REG_MCAN_TXBC register (little-endian): 00664866

Value from REG_MCAN_TXFQS register (little-endian): 00626666

Value from REG_MCAN_TXESC register (little-endian): 00646666

Value from REG_MCAN_TXBRP register (little-endian): 00666666

Value from REG_MCAN_TXBAR register (little-endian): 00686666

Value from REG_MCAN_TXBCR register (little-endian): 006A6666

Value from REG_MCAN_TXBTO register (little-endian): 006C6666

Value from REG_MCAN_TXBCF register (little-endian): 00664866

Value from REG_MCAN_TXBTIE register (little-endian): 00706666

Value from REG_MCAN_TXBCIE register (little-endian): 00664866

Value from REG_MCAN_TXEFC register (little-endian): 00786666

Value from REG_MCAN_TXEFS register (little-endian): 00664866

Value from REG_MCAN_TXEFA register (little-endian): 007C6666

your guidance on whether this method provides accurate insights into the device's configuration would be immensely helpful.

Regarding the series resistor in the schematic (R384), I can confirm that it is indeed 0 ohms. Despite its value, could its placement between the OSC2 pin and the crystal still potentially affect the stability of the oscillator circuit and introduce impedance mismatch?

Thank you once again for your assistance and valuable expertise.

Regards,

Hi Anand,

Thanks for the register information, however, I'm not sure they are correct just by looking at the values.  It appears the lower two bytes are always either 0x4866 or 0x6666 which would not be normal.  I've looked through a few of the registers such as the Nominal Bit Timing and Prescaler  (NBTP) and the timing does not work for a 500kb bit rate.

Can you try to verify these registers are being read back correctly?  The Device ID registers 0x0000 and 0x0004 should always return a known value.  Also the Test and Scratch Pad register 0x0808 can be used to write a value and then read it back to verify both the Read and Write SPI communication is working correctly.

Thanks and Regards,

Jonathan

Hi Jonathan,

I apologize for the delay in reaching out to you. I've been troubleshooting an issue,I have made progress in receiving CAN messages successfully from both PCAN and CanOe, I am encountering challenges with transmitting messages from the target device. TCAN4x5x controller is successfully receiving data from both PCAN and CanOe.

However, when attempting to send messages from the target device, the external receiver detects the message only once. Upon inspection, the received messages appear to lack any data payload.

I have attempted to read and write to the registers using the functions provided in the driver code. However, despite successfully writing to the Test register, the value read from the register remains at 0.

[    3.064191] tcan4x5x spi3.0: no CAN clock source defined
[    3.070293] tcan4x5x spi3.0: setup mode 0, 8 bits/w, 10000000 Hz max --> 0
[    3.088392] TCAN4x5x Device ID0: 0x32150320
[    3.092575] TCAN4x5x Device ID1: 0x87654321
[    3.098278] TCAN4x5x Revision: 0x0
[    3.102649] TCAN4x5x Status: 0xa33
[    3.106285] TCAN4x5x Error Status: 0x80
[    3.110203] TCAN4x5x Interrupt Flags: 0x80
[    3.110766] iio iio:device1: registered accelerometer lis2dw12
[    3.114373] TCAN4x5x Control: 0x0
[    3.123524] TCAN4x5x MCAN Configuration: 0x0
[    3.127801] Value read from TCAN4X5X_TEST_REG: 0

I look forward to your response.

Thanks & regards,

Anand 

Hi Anand,

Anand Kulkarni said:

I have attempted to read and write to the registers using the functions provided in the driver code. However, despite successfully writing to the Test register, the value read from the register remains at 0.

Are you referring to the "Test" register with address 0x1010?  If so, this is a read only register.  Or are you referring to the "Test Register and Scratch Pad" register with address 0x0808 that does support both Read/Write access?

Anand Kulkarni said:

However, when attempting to send messages from the target device, the external receiver detects the message only once. Upon inspection, the received messages appear to lack any data payload.

If I understand you correctly, the receiving devices (PCAN or CANoe) do see a message on the bus that is transmitted from the TCAN4550.  Does this message have the correct message ID and header bits based on what you are trying to transmit?  What is the DLC value in the message header?

I have seen one previous situation that sounds similar to yours where messages were not containing any message data.  It turned out that the SPI communication was using multi-word writes when placing the message data into the TX Buffer element in the TCAN4550's MRAM.  However, the SPI chip select signal was transitioning high in between every 32-bit data word which was causing the SPI multi-word write to fail.  Only the first 32-bit word in the transaction that contained the message ID was getting placed into the TX Buffer.

Do you have the ability to monitor the SPI signals with a logic analyzer?

Can you read back the memory contents of the TX buffer that is being used to transmit the message?  If so, can you read it back and verify it matches the contents of your message including the correct DLC and data bytes?

You can find the MRAM TX Buffer Element definition in section 2.4.3 of the M_CAN User's Manual published by Bosch (Link).

Regards,

Jonathan

Hi Jonathan,

Thank you for your detailed response and suggestions, To clarify, I have been referring to the "Test Register and Scratch Pad" register with address 0x0808, not the "Test" register at address 0x1010. 

Regarding the reception of messages from the TCAN4550, received messages lack any data payload, and the message ID does not match the expected values. The DLC value in the message header is also not as expected. Image below shows the receiver trace window.

I am currently working on monitoring the SPI signals between data transfers using a logic analyzer to identify any anomalies.

Additionally, I attempted to read the memory contents of the TX buffer being used to transmit the message. However, the data I retrieved from the M_CAN TX buffer did not match the expected contents of the message.

I was sending messege with ID 123, data 12345678, and this is what I was getting from the FIFO
[ 145.924597] Transmit FIFO Data[0]: 00000000

I would greatly appreciate any additional suggestions or insights you may have, Looking forward to your response.

regards,

Anand Kulkarni

Hi Jonathan,

I also want to mention one observation here, In our system, we utilize an external crystal with a frequency of 20 MHz. To accommodate this, I made the necessary adjustments by changing the clock definition in the tcan4x5x-core.c file from 40 MHz to 20 MHz. Consequently, this alteration enabled successful message reception within our system.However, upon conducting loopback testing, I noticed a same discrepancy in the results. Specifically, when performing loopback testing with the 20 MHz clock configuration, the received message appeared same as it is showing on the PCAN view trace : can0 000 [0] 

This outcome contrasts with the expected behavior observed when the clock was defined at 40 MHz. Under the previous configuration, loopback testing yielded the anticipated results.

But with 40 Mhz clock defined, when attempting to send messages externally and then receive them, it displays bus-off followed by bus-heavy conditions on the PCAN and CanOe.

Hi Anand,

If you are unable to write and read back a value from the Scratchpad register 0x0808, and all your other read backs are returning "0's" when you try to read back the TX Message data, then I'm not sure whether it is just an issue with a write, read, or both functions.  It seems like there may be some issue with your SPI communication. 

It appears like something is working because it you are seeing some device activity, but the odd behavior could be from some sort of SPI errors.  It would be good to verify the SPI signals with a logic analyzer or scope plot to see if there are any errors with them. A clock problem could also cause SPI communication errors. 

If you notice, there are 3 different groupings of registers with different address ranges.

The registers in the group with address 0x0000 to 0x002F are implemented in logic and only require the SPI clock.  They do not require the system clock supplied through the OSC1/2 pins to be active or working properly to interact with.

The registers in the group with address 0x0800 to 0x08FF are device related registers not associated with the MCAN controller.  They do require the system clock to be functional so that the digital core can act upon the register read/write request coming in from the SPI bus.

The registers in the group with address 0x1000 to 0x10FF are MCAN related registers are part of the Bosch MCAN IP.  These registers also require the system clock to be functional in order to access the registers as well as to send or receive CAN messages.

There is a FIFO that handles the SPI clock domain to System clock domain translation on the SPI read/write data.  If the system clock has an issue, then there will be an error getting data through the FIFO and this will be reported in the Status register 0x000C that only operates off of the SPI clock domain.

Can you read the registers 0x0000 to 0x0010?  Can you also try to write to register 0x0010 and read back the value you just wrote?  At the same time can you try to do the write/read test on the scratchpad register 0x0808 again to see if it still has an issue?  If the Sratchpad register doesn't work, but the other registers work then we may be able to conclude this is a clock issue.  If you also have issues with the registers 0x0000 to 0x0010 then there may be a protocol issue with your SPI signals.

For the CAN message reception, I am confused a little and I'm not sure I understand.  In your first post today you mentioned that your received messages lacked any data payload and had an incorrect message ID.  But in your second post, you said that you made alterations to the clock configuration and this enabled successful message reception within our system.  Does that mean that the received messages contained the correct data payload and message ID after the clock configuration adjustment?

What adjustments did you make?  Can you try again to get me a list of register values for the device?  The last time it appeared the registers had an incorrect value so I'm still not quite sure about the configuration you are using.

Do you have the ability to capture the CAN messages on a scope for both the messages transmitted from the TCAN4550 and to the TCAN4550 from PCAN or CANoe?

Regards,

Jonathan