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DP83869HM: 1588 SFD pulse width clarification

Steven Hansen
Intellectual 601 points
Part Number: DP83869HM
Other Parts Discussed in Thread: AM6442, DP83869

Hi all,

I asked this question a week ago, but only now realize I don't understand the accepted answer.

We are looking to use DP86839's GPIO_0 and GPIO_1 pins for 1588 hardware timestamping of TX and RX SFD. To do this we are configuring GPIO_0 using 0x1E0[3:0] = 0x6 = Receive SFD, and GPIO_1 using 0x1E0[7:4] = 0x5 = Transmit SFD. Our timestamp device (AM6442 CPTS) requires a minimum 98ns pulse width.

Q1. Can the SFD pulses on GPIO_0 and GPIO_1 be extended to ensure they are >98ns wide?

Q2. In the previously linked answer, I was told to use 0x1E0[7:4] to adjust SFD pulse timing in 8ns increments. But the datasheet shows 0x1E0[7:4] is for GPIO_1_CTRL. Was this a mistake? Is there another register to adjust the pulse timing for TX/RX SFD on GPIO_0 and _1?

  • 0
    TI__Mastermind 19755 points

    Hi Steven,

    Please look at the comments below:

    Q1: SFD pulses on GPIO_0 and GPIO_1 should be in us range, it should be greater than 98ns

    Q2: Thank you for pointing it out. Yes, this is a mistake on our side.

    8ns are mainly the SFD variation on the baseline latency. Please refer to session 9.3.2.1 for further information:

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Intellectual 601 points

    Thank you, I didn't realize SFD was held high for such a long duration, that should be fine for our application.

    On Page 24 the datasheet for DP83869 says:

    The exact timing of the pulse can be adjusted through register. Each increment of phase value is an 8-ns step

    Can you clarify what this means? What timing adjustment is possible for SFD, and what register should be used for adjustment?

  • +1 in reply to Steven Hansen
    TI__Mastermind 19755 points

    Hi Steven,

    Thank you for pointing it out. It seems like our datasheet is not too clear. Hope the following response could help you to clear up the confusion.

    We are adjusting baseline latency to help with the SFD variation based on customer's system. the baseline latency has increment of phase value 8ns.

    --

    Regards,

    Hillman Lin