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DS250DF410: Retimer for 25G interface

Mohamed Sahal C
Prodigy 60 points
Part Number: DS250DF410
Other Parts Discussed in Thread: DS560MB410, DS280BR820, , DS250DF230

Hi,

I am current working on a project where I need to have a 25G interface between an FPGA and SFP28 module. The trace length is coming around 7.5 inches with a simulated insertion loss of around 10 dB (using FR408HR material).

Which device is suitable here to use? Redriver is enough or Retimer is required? (I want to use same FR408HR material only for cost reduction)

Can I place the retimer close to the SFP module so that loss towards the SFP side is around 2-3 dB?

Regards,

Sahal

  • 0
    Prodigy 60 points

    Does DS250DF410 support CPRI data rate of 9.8304?

  • 0 in reply to Mohamed Sahal C
    TI__Mastermind 20192 points

    Hi,

    A redriver such as DS280BR820 or DS560MB410 can equalize 10 dB of loss, but keep in mind that a redriver will only equalize jitter due to ISI.  A redriver will not compensate for Rj, or any impairments due to reflections.  I'd recommend simulation with our device IBIS-AMI models in order to better evaluate if a redriver will be suitable for your application.

    The DS250DF410 has a high minimum CTLE boost of around 7-9 dB.  Based on empirical testing, I'd recommend a minimum of 3 dB of loss between the SFP module and the DS250DF410 receiver.

    The DS250DF410 will not lock to a 9.8304 Gbps signal as this is outside of its CDR lock range.  The DS250DF410 can support this rate through CDR bypass, but the ability to control TX amplitude is more limited in CDR bypass since TX FIR settings are not applied.  This can pose a challenge for SFF-8418 compliance in CDR bypass.

    For an application supporting CPRI, I'd recommend considering the DS250DF230.  This device has a CDR lock range support 9.8304 Gbps.  It also has an option to bypass one of the CTLE stages, allowing for a minimum CTLE boost of around 0.6 dB.  Additionally, this device has better support for adjusting VOD in CDR bypass case.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 60 points

    Ok. Thanks.

    Does the CAL_CLK_IN need to be in sync with the data for PTP or syncE applications? Can I give from a separate local oscillator?

    I have a 3.3V CMOS oscillator, can I use a resistor divider circuit to get 2.5V LVCMOS clock for CAL_CLK_IN?

  • 0 in reply to Mohamed Sahal C
    TI__Mastermind 20192 points

    Hi Mohamed,

    CAL_CLK_IN does not need to be in sync.  This clock is not used for retiming the data.  Retimed data is based on the recovered clock from the data signal.

    Yes, you can use a resistor divider to get 2.5V LVCMOS.

    Thanks,

    Drew