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DP83867CR: Ethernet Compliance Testing for 1000baseT

Ishan Padaliya
Prodigy 180 points
Part Number: DP83867CR

Hello TI team,

We are using DP83867CR, for Compliance testing we are referring this document : https://www.ti.com/lit/an/snla239c/snla239c.pdf?ts=1707443888787

We are able to set 10baseT, and 100baseT, for compliance testing.

Whenever we apply below commands for 1000baseT, FDX, it setting 10baseT, HDX only.

=> 
=> 
=> mii info
PHY 0x00: OUI = 0x80028, Model = 0x23, Rev = 0x01, 1000baseT, FDX
=> mii write 0 1f 0x8000
=> mii write 0 09 0x5B00
=> mii write 0 25 0x0480
=> mii write 0 1f 0X4000
=> 
=> 
=> mii info
PHY 0x00: OUI = 0x80028, Model = 0x23, Rev = 0x01,  10baseT, HDX
=>


please guide us on the same, to set 1000baseT, FDX for compliance testing.


Thanks and Regards,
Ishan

  • 0
    TI__Mastermind 19755 points

    Hi Ishan,

    May I ask if you are seeing any issue with test mode 2 during compliance test? May I ask which register are you reading the speed on?

    Test mode 2 is mainly testing on the jitter in compliance. Form my understanding, the speed  register will not be properly update since the PHY is configure in special compliance test mode.

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 180 points

    Hi  Hillman Lin,

    Thanks for the replay,

    As mentioned above, for the compliance testing we are using below registers, let me know if we are missing anything.
    as we are following above mentioned document. These are the steps that we understand to follow to configure the PHY.





    These is no register Reg 0x1D5 in datasheet, which is needed to configure the Test Mode 1, 

    And for test mode 2 and test mode 4, we are getting same response, It's getting configured in 10baseT, HDX.


    1) mii write 0 1f 0x8000

    Software Reset:
    1 = Perform a full reset, including registers.
    0 = Normal operation.


    2) mii write 0 09 0x5B00

    010 = Test Mode 2 - Transmit Jitter Test (Master Mode)

    Enable Manual Master / Slave Configuration:
    1 = Enable Manual Master/Slave Configuration control.

    Manual Master / Slave Configuration Value:
    1 = Set PHY as MASTER when register 09h bit 12 = 1.

    Advertise 1000BASE-T Full Duplex Capable:
    1 = Advertise 1000Base-T Full Duplex ability.

    Advertise 1000BASE-T Half Duplex Capable:
    1 = Advertise 1000Base-T Half Duplex ability.


    3)  mii write 0 25 0x0480
    If bit 7 is set then Test mode is driven on all 4 channels.

    4) mii write 0 1f 0X4000



    Thanks and regards,
    Ishan

  • 0 in reply to Ishan Padaliya
    TI__Mastermind 19755 points

    Hi Ishan,

    Thank you for sharing the information. I will review it and provide you an response by tomorrow.

    --

    Regards,

    Hillman lin

  • 0 in reply to Hillman Lin
    TI__Mastermind 19755 points

    Hi Ishan,

    Are you not able to run the the compliance test successfully?

    May I ask which speed status are you reading? Again, from my understanding the special compliance test mode does not reflect on the speed status register since the PHY is not link up or communicate with any link partner during compliance test mode. May I ask why is this a concern?

    Thank you for pointing it out. 0x01DF is a register that bring DP83867PHY from low power saving mode to compliance mode. will update this register in the new revision of datasheet in the future.

    --

    Regards,

    Hillman Lin