DP83867IS: Link unstable

Hi Floris,

Thank you for sharing the information. May I ask what did you mean by not stable link.

Are you able to link up at all with DP83867PHY? If so, how often does the link drop and does the link go back up?

If so, could you share a register dump from 0x0000 to 0x001F of both link up case and no link up case

If possible, could you also share the block diagram of your system? What is the link partner PHY? and what is the cable length.

Here are the debug appnote that might be helpful to you:

https://www.ti.com/lit/an/snla246b/snla246b.pdf?ts=1710351163145&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83867IS

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Regards,

Hillman Lin

Link is established for a short time and then is lost again. Uptime of the link varies randomly from less than 1 second to several minutes.

0000:1140
0001:796D
0002:2000
0003:A231
0004:0101
0005:C1E1
0006:006F
0007:2001
0008:4CE9
0009:0000
000A:0800
000B:0000
000C:0000
000D:401F
000E:0000
000F:3000
0010:5008
0011:6C02
0012:0000
0013:1C42
0014:29C7
0015:0000
0016:0000
0017:0040
0018:695B
0019:4444
001A:0002
001B:0000
001C:0000
001D:0000
001E:0002
001F:0000

0000:1140
0001:7949
0002:2000
0003:A231
0004:0101
0005:0000
0006:0064
0007:2001
0008:0000
0009:0000
000A:0000
000B:0000
000C:0000
000D:401F
000E:0000
000F:3000
0010:5008
0011:0002
0012:0000
0013:0000
0014:29C7
0015:0000
0016:0000
0017:0040
0018:695B
0019:4444
001A:0002
001B:0000
001C:0000
001D:0000
001E:0002
001F:0000

partner PHY in the setup is Marvell 88E6185, but our system must also work with other partner PHYs. 

Cable length of ca. 4m gives the worst results. Increading to ca. 5m results in more uptime of the link. Connecting a switch instead of the 88E6185, with a 2m cable seems to result in a stable link.

FYI we have also done compliance test using test mode 5, measured on 100ohm termination resistors at quadrax connector, and failed on AOI template because of output voltage (+/-830mV -> must be 950 to 1050mV).

We are mainly testing on the ethernet interface through the MUX, but are experiencing identical issues on the interface on the other DP83867 PHY.

Hi Floris,

Could you try to following script and see if you are able to fix the unstable link up?

• Write register 0x01D5 to F508
• Make sure use extended register method when writing register 0x01D5:
  • https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1271487/faq-extended-register-space-access-for-ethernet-phys?tisearch=e2e-sitesearch&keymatch=extended%2520register#

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Regards,

Hillman Lin

Hi Hillman Lin,

We tried your suggestion but it did not solve the issue. Link is still only up for a fraction of a second before it drops again.

Best regards,

Floris

Hi

Connecting we connected 2 of our devices together. It is depending on the cable length if the link is successful or not. 

Regards, 

Floris

Hi Floris,

When you said it depend on cable length, could you be more specific on this scenario?

If you are using short cable, could you try the following script on session 3.8 and see if you are able to link up?

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Regards,

Hillman Lin

Hi 

The problem occurs on cable length of around 4m. I don't think that is categorized as "short" cable. Nevertheless, we already tried the script in section 3.8 and it did not result in any improvement.

Best regards

Floris

Hi Floris,

If possible, could you provide some more detail on your observation:

• When you said link down, are you seeing any cable length less than 4m you will see a link down?
• Could you probe the MDI lines when the PHY is link up and link down?
• What kind of cable are you seeing this issue?
• If possible, could you read register 0x0225 when you see a link up?

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Regards,

Hillman Lin

Hi

- We have not noticed this issue on cable length less than 4m, but we have not tried with a lot of different cable lengths less than 4m. 
- When probing the MDI lines in setup where links drops, we see following steps being repeated: NLPs, followed by MLT3 symbols, followed by an idle line.
- cabling:
Unit 1 -- Quadrax (ca. 2m) --> patch panel --> Cat5e/Cat6 --> patch panel --> Quadrax (ca. 2m) --> Unit 2 
Changing total cable length is done by inserting other length of cable for the patch panel connection.
- We have have cyclically polled the data of register 0x0225 during link up and got random values between 0x0023 and 0x0468.

according to https://www.ti.com/lit/an/snla246b/snla246b.pdf values should be converted to decimal (35 -> 1128) and checked with the MSE ranges, which means our link ranges from excellent to poor. 

Distribution is as follows:

Note that this includes values several re-established links.

With the longer cable where we have a stable link values range from 0x015A (346 decimal) to 0x0482 (1152) with following distribution:

values in registers 0x265, 0x2A5 and 0x2E5 were constant on 0x7FFF.

As stated earlier, we noticed bit 7 of 0x0031 being '1' after start-up and reset, although RX_CTL is strapped to mode 3. Can you confirm that this is normal behavior? Do we need to clear this bit to enter normal operation?

Furthermore, we measured clocking of the device. We have 53ps RMS jitter on X_I oscillator. Is this acceptable for the device?

Best regards

Floris

Hello,

Hillman is OoO today and will be back tomorrow.

Sincerely,

Gerome

Hi Floris,

Thank you for sharing this detail information. 

Just want to confirm. Does this issue only occur when the cable is greater than 4m or only seeing this issue around 4m cable?

If my understanding is correct, you are seeing poor MSE value when the cable reach 4m? Cable greater than 4m or less than 4m you are not seeing this issue? 

• If that is the correct understanding, could you try another DP83867PHY as link partner and see if you are observing this issue?
• May I ask what cable are you using? If possible, could you run a TDR test on 4m cable and make sure this cable is under a good condition? You can also switch to another cable and see if that change the result?

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Regards,

Hillman Lin

That is correct. We would need to redo the test for longer cables. I will get back to you with more information on that tomorrow.

Link issues persist between 2 DP83867 phys as well. 

Cabling consist of 2 parts of quadrax cable (ca. 2m), connected by a patch cable (CAT5E). I will come back to you with more information on TDR tomorrow. 

Hi Floris,

Thank you for your reply. I will wait for your result.

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Regards,

Hillman Lin

Hi Hillman,

We see the issue as well with longer cable (ca. 20m)

Following register values were acquired as instructed by https://www.ti.com/lit/an/snla334/snla334.pdf.
Setup is: 2 units (with DP83867IS) connected to eachother, of which 1 is not powered.

0x0190	0x1F11
0x0191	0x0000
0x0192	0x1100
0x019A	0x3A12
0x019B	0x0000
0x019C	0x1400
0x01A5	0x0021

Best regards

Floris

Hi Floris,

I am not sure if I understand your setup completely. Please correct me if I am wrong:

• DUT: DP83867IS < -- > Link Partner: DP83867IS (Not power up)
  I don't think you will see a link when Link Partner is not power up. Please correct me if I misunderstand something.

May I ask what are those register provided? Did you also have the MSE register value for 20m (0x0225)?

If you are also seeing this poor SQI value and unstable link in, than it is most likely the layout constraint. I also attach the layout checklist below hope this could help you 

1524.Industrial_PHY_Layout Review Checklist.xlsx

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Regards,

Hillman Lin

The setup is correct. Link partner was not powered to ensure Link is down (as required in Time Domain Reflectometry with DP83867 and DP83869 §1 "TDR can be used only when the Link is down."). So obviously I did not expect to see a link during TDR.

The registers I provided are the "TDR Register Results" according the application note. Is this not what you asked for?

I also attach the layout checklist to review.

Regards,

Floris4237.Industrial_PHY_Layout Review Checklist.xlsx

Hi Floris,

Thank you for your feedback. I will take a look and get back to you tomorrow.

Currently, still in a discussion with the team. I might need to provide you an response on Wednesday.

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Sincerely,

Hillman Lin

Hi Floris,

Thank you for sharing the information. 

I discuss with the team and there are something I would like to confirm on our side.

Based on the block diagram you provided below, we see that there are MUX on the MDI lines.

If possible, we would like to confirm did you still see the unstable link up on the upper PHY without the MUX on the MDI lines? We normally don't recommend any MUX on the MDI lines because this have an effect on the impedance matching. 

If possible, could you send us the schematic around the MDI lines for us to review internally?

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Regards,

Hillman Lin

Hi Hillman

I tried connecting with the upper PHY with different cable lengths and was not able to reproduce the problem (link was always stable). Note that also other factors are different in this setup (eg. distance to transformer is noticeably shorter).

I will send you the schematic in person. I just now noticed that in the latest revision of the datasheet the RSVD pins are advised to be connected to VCC, while they are unconnected on our schematic.

Regards,

Floris

Hi Floris,

May I ask what is the RSVD pin you are referring to?

Again, we typically don't recommend customer to have TMUX in between the MDI lines due to the impedance matching and common voltage voltage. 

• If possible, could customer try TMUX on the other side of the transformer?
• Could customer also check is TMUX pulling the MDI lines to certain DC voltage? This will have an huge effect on the link up.

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Regards,

Hillman Lin

Hi Hillman

I was referring to pins 1 & 10 of TMUX4212.

• TMUX on other side of the transformer is not feasable
• TMUX is not pulling MDI lines to certain DC voltage. We are currently only working with offset provided by the DP83867IS and no second ethernet channel connected to the TMUX. Note that in the future we will require DC offset through the magnetics center tap to ensure the TMUX being operated in its allowed region (NLPs on not-selected channel would pull signal below 0.5V).

Regards,

Floris 

Hi Floris,

If possible, could you share the schematic around the MDI lines to review. DC offset is not allow on the MDI lines for DP83867. If DC offset is required, we recommend connected on the other side of transformer. 

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Regards,

Hillman Lin

Hi

Please check your private messages.

Regards,

Floris

Hi Floris,

In the case where you are able to see a temporary link. Could you read the 0x225 to see the link quality. One of the hypothesis is adding TMUX in between the MDI lines has an effect on the impedance which decrease the link quality.

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Regards,

Hillman Lin

Is that not what I did 16 days ago? Setup has not changed since then.

Hi Floris,

Sorry for asking multiple times.

If possible, could you probe the waveform with TMUX and without TMUX case on the MDI lines?

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Regards,

Hillman Lin

Hi Hillman,

We are currently suspecting excessive crosstalk in the transformer to be the root cause of this issue. We will first investigate this further. 

Thank you for your support. 

Best regards

Floris

Hi Floris,

Understood, thank you for the update.

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Regards,

Hillman Lin