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Original question:

TCAN4550EVM: Unsupported Version 0, while interfacing with Linux board.

TCAN4550EVM: Unsupported Version 0, while interfacing with Linux board.

Sai Kiran Y
Prodigy 60 points
Part Number: TCAN4550EVM
Other Parts Discussed in Thread: TCAN4550

Hi,

Continuing from the linked question. I tried to check if there is any issue with the SPI on the Linux board I was using. I did not find any issue there. Have got Logic Analyzers and tried capturing those waveforms. Here is the link to the waveforms. I see that MISO is always LOW. I am not sure if this is expected. There is some data on MOSI. 

Thanks,

Sai Kiran.

  • 0
    TI__Mastermind 22170 points

    Hi Sai Kiran,

    I'm not able to access google drive due to our IT department's file sharing security policy.  Can you insert the files to this thread individually or as a compressed zip folder?  Or even take a screen capture and paste it into this thread?

    Thanks and Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Mastermind 22170 points

    Hi Sai Kiran,

    For your reference of what the SPI signals should look like, I would point you to the datasheet SPI Write and Read figures which shows the requirements. The chip select signal (nCS) should transition low and remain low for the entire read/write transaction.  The TCAN4550 will count the clock cycles to make sure it is both a multiple of 32 (or 1 word of data), and the data portion is equal to the number in the "Length" field of the header.  The first word, or 32-bits, contains the read/write op code of 0x41 or 0x61, followed by the register or MRAM address, and then the Length or number of registers or words of data to read/write in this transaction.  The datasheet figures show length of 2, so two registers are being accessed in each figure.  If you only wanted a single register, you would just set the Length value to 0, and then only have 64 clock cycles while the nCS signal was low.  If there is an incorrect number of clock cycles, then the device will discard a SPI Write and set the SPI Error flag.  If this happens on a read, the device will set the SPI Error flag to indicate the data transmitted on the SDO pin could be incomplete or corrupted. It is common to see that the MCU will pull the nCS signal high after every 8, 16, or 32 bits which will cause a SPI error and some modification to the nCS signal in the firmware driver may be necessary.

    Here is a scope and logic analyzer capture I made of actual signals for a read of register 0x0000. This controller transmitted 8-bits at a time but the important factor is that the chip select remained low for the entire 64-bits.

    The TCAN4550 also only supports SPI Mode 0, so you may need to verify the clock edge is correctly aligned with the data.

    Regards,

    Jonathan