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DP83867ERGZ-R-EVM: Tx data, but does not Rx?

Keith Mattson
Prodigy 40 points
Part Number: DP83867ERGZ-R-EVM

Connected to XILINX ARTIX7 FPGA

Ran external connections @ 1GbE to Wireshark on laptop. Tx good, Rx nogo

Tried loopback, crossing A - B @ 100MbE, directly connected at RJ45. Tx good, Rx nogo

In both situations, Ethernet signals are measured at the PHY chip, the Rxclk is active 2.5MHz, but no signals on RxD0-3?

Are there registers in PHY chip preventing this output back to FPGA? Physically do not measure anything coming out on a scope? This occurs on 2 different boards, and have replaced the PHY on 1 of those, so 3 PHY chips.

Thx!

  • +1
    TI__Genius 13792 points

    Hi Keith,

    Can you clarify the loopback configuration you are setting (both H/W and registers)?

    After writing 0x0[14] = '1' to enable MII loopback, do you see RX data after TX data is input to the PHY?

    The PHY is outputting the incorrect RXCLK frequency for 100/1000M, but this should not affect the ability for the data to loopback (with errors).

    If no link partner is being used to negotiate to the speed used by the MAC, register 0x0[13,12,6] can be used to disable auto-neg and force a speed for the appropriate RXCLK output.

    Thank you,

    Evan