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DP83826E: DP83826E and STM32H7 data transmission problem

Louis kia
Prodigy 10 points
Part Number: DP83826E

Hello,

I'm encountering an issue while interfacing the DP83826 with my STM32H74 using LWIP.

  • I'm operating in RMII basic mode,
  • and while some boards with identical software (web server, TCP, UDP, etc.) are functioning correctly, many are facing the same problem.
  • I'm observing incoming RX signals during ARP with my PC's IP and MAC addresses in debug mode. However, I'm only sporadically seeing signals in TX_D0 and TX_EN.
  • I've confirmed that the MDIO and MDC signals are functioning correctly based on register readings. Additionally, soldering appears to be fine.
  • The output clock frequency 50MHz ok (derived from a 25MHz input), and the link is established.
  • No ARP or IP request on wireshark from the board

Could you please assist me in debugging this issue? rx then tx

Also, I'm wondering if there's a way to test the PHY layer, perhaps through a loopback test? If so, which loopback method would you recommend?

Dev addr 0x1    =>REG :0x467 value 0x97 151     0000000010010111
Dev addr 0x1    =>REG :0x468 value 0x195        405     0000000110010101
Dev addr 0x1    =>REG :0x0 value 0x3000 12288   0011000000000000
Dev addr 0x1    =>REG :0x1 value 0x786d 30829   0111100001101101
Dev addr 0x1    =>REG :0x2 value 0x2000 8192    0010000000000000
Dev addr 0x1    =>REG :0x3 value 0xa111 41233   1010000100010001
Dev addr 0x1    =>REG :0x4 value 0x1e1  481     0000000111100001
Dev addr 0x1    =>REG :0x5 value 0x4de1 19937   0100110111100001
Dev addr 0x1    =>REG :0x6 value 0x7    7       0000000000000111
Dev addr 0x1    =>REG :0x7 value 0x2001 8193    0010000000000001
Dev addr 0x1    =>REG :0x8 value 0x0    0       0000000000000000
Dev addr 0x1    =>REG :0x9 value 0x0    0       0000000000000000
Dev addr 0x1    =>REG :0xA value 0x102  258     0000000100000010
Dev addr 0x1    =>REG :0xB value 0x9    9       0000000000001001
Dev addr 0x1    =>REG :0xC value 0x0    0       0000000000000000
Dev addr 0x1    =>REG :0xD value 0x401f 16415   0100000000011111
Dev addr 0x1    =>REG :0xE value 0x195  405     0000000110010101
Dev addr 0x1    =>REG :0xF value 0x0    0       0000000000000000
Dev addr 0x1    =>REG :0x10 value 0x215 533     0000001000010101
Dev addr 0x1    =>REG :0x11 value 0x10b 267     0000000100001011
Dev addr 0x1    =>REG :0x12 value 0x6400        25600   0110010000000000
Dev addr 0x1    =>REG :0x13 value 0x2800        10240   0010100000000000
Dev addr 0x1    =>REG :0x14 value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x15 value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x16 value 0x100 256     0000000100000000
Dev addr 0x1    =>REG :0x17 value 0x65  101     0000000001100101
Dev addr 0x1    =>REG :0x18 value 0x400 1024    0000010000000000
Dev addr 0x1    =>REG :0x19 value 0x8c01        35841   1000110000000001
Dev addr 0x1    =>REG :0x1A value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x1B value 0x7d  125     0000000001111101
Dev addr 0x1    =>REG :0x1C value 0x5ee 1518    0000010111101110
Dev addr 0x1    =>REG :0x1D value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x1E value 0x102 258     0000000100000010
Dev addr 0x1    =>REG :0x1F value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x20 value 0x3000        12288   0011000000000000
Dev addr 0x1    =>REG :0x21 value 0x786d        30829   0111100001101101
Dev addr 0x1    =>REG :0x22 value 0x2000        8192    0010000000000000
Dev addr 0x1    =>REG :0x23 value 0xa111        41233   1010000100010001
Dev addr 0x1    =>REG :0x24 value 0x1e1 481     0000000111100001
Dev addr 0x1    =>REG :0x25 value 0x4de1        19937   0100110111100001
Dev addr 0x1    =>REG :0x26 value 0x5   5       0000000000000101
Dev addr 0x1    =>REG :0x27 value 0x2001        8193    0010000000000001
Dev addr 0x1    =>REG :0x28 value 0x0   0       0000000000000000
Dev addr 0x1    =>REG :0x29 value 0x0   0       0000000000000000

[low_level_init:377]
ETH_MOD FULL DUPLEX

[low_level_init:378]
ETH_SPEED 100M
[low_level_init:420]LINK Up !
[ethernetif_input:540]----------STARTING ETHERNETIF_INPUT-----etharp_request: sending ARP request.
etharp_raw: sending raw ARP packet.
ethernet_output: sending packet 0x1002000c


[low_level_output:462]Sendig !! etharp_timer

MX_LWIP_Init done
[tcp_server_init:105]create TCP
[tcp_server_init:108]create TCP  PCB done
[tcp_server_init:115]tcp_bind done 0
[tcp_server_init:121]start tcp listening for _pcb
[tcp_server_init:125]initialize LwIP tcp_accept callback functionethernet_input: dest:0hx:0hx:0hx:0hx:0hx:0hx, src:0hx:0hx:0hx:0hx:0hx:0hx, type:ff
etharp_update_arp_entry: 192.168.1.1 - "MY PC MAC ADDRESS HERE"
etharp_find_entry: found empty entry 0
etharp_find_entry: no empty entry found and not allowed to recycle
etharp_input: incoming ARP request
etharp_input: ARP request was not for us.

  • 0
    TI__Mastermind 24988 points

    Hi Louis,

    Thanks for your query!

    The setups are all identical in HW, SW, and application setup (IP/MAC address)?

    Do you see any difference in the PHY register dumps between the working and failing setups?

    For loopback on the PHY's MDI side, write register 0x16[4:0] = 10h (reverse loopback) .

    For loopback on the PHY's MAC side, write register 0x0[14] = 1h (MII loopback) .

    Best regards,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 10 points

    Evan Thank you for your answer ,

    The setups are all identical in HW, SW, and application setup (IP/MAC address)? Yes

    Do you see any difference in the PHY register dumps between the working and failing setups? No all are the same

    For loopback on the PHY's MDI side, write register 0x16[4:0] = 10h (reverse loopback) . ?

    For loopback on the PHY's MAC side, write register 0x0[14] = 1h (MII loopback) .


    Could you clarify what I should expect when enabling loopback? Is it necessary to connect a cable to a partner device?


    I'm always facing this problem. Could you provide some other solution please? 

  • 0 in reply to Louis kia
    TI__Mastermind 24988 points

    Hi Louis,

    This is strange, I expect some link down or some other status bit difference between working/failing setups.

    Clarifying on the loopback tests:

    For MII loopback, no link partner is required. After setting loopback, send data from DP83826's MAC and check if the same packets are received to validate the MAC-side connection.

    For reverse loopback, link partner is required. After setting loopback, send data from STM32H4's MAC and check if either the STM32H74 or its MAC receives the same signals looped back from DP83826.

    Please also test with this register script on DP83826, there are some configs here that may help with IOPT consistency:

    DP83826_IOPT_Script.txt

    Thank you,

    Evan