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DP83822I: Regarding hardware bootstrap pin Connections

Yogesha D G
Prodigy 70 points
Part Number: DP83822I

Tool/software:

Hi Team,
We have interfaced PHY DP83822IRHBT to the NXP controller MIMXRT1176CVM8A in RMII Master mode configuration.
We have connected the Boot strap pins of PHY as per below table.

Boot strap pins Connected in Schematics as below Pull up/Pull down connected
COL NC since RMII master mode No
RX_D0 Controller's MAC's Receive pin No
RX_D1 Controller's MAC's Receive pin No
RX_D2 NC since RMII master mode No
RX_D3 NC since RMII master mode No
LED_0 Connected to LINK LED of LAN Connector No
LED_1 Connected to SPEED LED of LAN Connector No
CRS Controller's MAC's CRS pin No
RX_ER NC since RMII master mode No
RX_DV Controller's MAC's DV pin. No

In Section 8.5.1 of PHY datasheet it is mentioned as below:

My question is: 
As per the above image, configuration of PHY can be done via Serial management interface and we are planning to use this option instead of 4-level hardware boot strapping. In this case, are the connections of the boot strap pins as per the above table, acceptable?

  • 0
    TI__Genius 12397 points

    Hi Yogesha,

    Yes, default straps are acceptable in this case for SMI access to configure PHY.

    However, there are two straps to keep in mind for register access:

    1) PHY address strap. If SMI bus is shared with another PHY at same address, then register access may be affected.

    2) XI strap. If the PHY is set to expect 50M input clock, register access will not work with a 25M XI.

    If the MAC drives these strap pins during start-up, it's possible the incorrect strap configuration will be set and affect register access.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    Prodigy 70 points

    Hi Evan,

     

    For Point 1:

    SMI bus is interfaced to only one PHY. There is no other PHY which is sharing the SMI interface of MAC. Hence, our understanding is that the first point that you have raised wont affect us.

     

    For point 2:

    I believe you are speaking about the below Bit 7 of 0x0017 RMII and Status Register (RCSR). 

    We have connected 25MHz crystal for PHY and operating using RMII Master Mode. In this mode, our understanding is that the PHY generates the 50MHz clock for the MAC. 

    I could not understand your statement of "PHY is set to expect 50Mhz input clock"

     

    Please clarify on these two points.

  • 0 in reply to Yogesha D G
    TI__Genius 12397 points

    Hi Yogesha,

    For point 1, thank you for clarifying this is the only PHY on the SMI bus - there is no concern here.

    For point 2, I was noting a possible concern to keep in mind if RMII slave mode is intended. As this application is using RMII master mode with 25M XI default setting, there is no issue here.

    Hope this helps,

    Evan