DP83TC814S-Q1: About LED Configuration Question

Part Number: DP83TC814S-Q1
Other Parts Discussed in Thread: DP83TC812EVM-MC

Tool/software:

Hello TI Team,

LED0 has the function of Link-OK indication.

Does it output blink_rate when it links OK?

Now, we can't measure the blink rate when it links ok.

How to configurate the function?

Below is our schematic:

Best Regards!

  • Hi Jingkun,

    Can you provide a screenshot of your LED0 schematic?

    By default, LED0 should typically be HIGH when link is up and LOW when link is down.

    If it is blinking and you have not changed the register settings, it may be linking up and linking down. Can you read register 0x1 multiple times to confirm the link status?

    You can configure LED0 to blink by setting the LEDS_CFG_1 registers as shown above. Register settings are changed via MDIO/MDC on the DP83TC814. 

    Best regards,

    Melissa

  • Hello Melissa,

    Below is  LED0 schematic.

    If the LED0 is blinking, it indicates that PHY is linking.

    If it links up, LED0 will output high. Is it right?

    Best Regards!

    Wang Jingkun

  • HI Jingkun,

    I don't see an LED connected to the LED0 pin on the DP83TC814. Is this correct?

    Yes, if there is link, LED0 will output high.

    Best regards,

    Melissa

  • Hello Melissa,

    Yes, it doesn't have an LED connected to the LED0 pin.

    Best Regards!

  • Hello Melissa,

    When LED0 pin added the pull up resistance (2.49k) to set the DUT as master mode.

    I read the register 0x1,  the bit2=1,  but the LED0 pin didn't output high.

    Why?

    Best Regards!

  • Hi Jingkun,

    If you probe LED1 during link up, what do you see?

    Can you read back registers 0x0-0x1F and 0x45D? 

    Best regards,

    Mellissa

  • Hi Mellissa,

    Below is read back register's value:

    0x00 : 0x2100
    0x01 : 0x0065
    0x02 : 0x2000
    0x03 : 0xa261
    0x04 : 0x0001
    0x05 : 0x0000
    0x06 : 0x0000
    0x07 : 0x2001
    0x08 : 0x0000
    0x09 : 0x0000
    0x0A : 0x0100
    0x0B : 0x0000
    0x0C : 0x0000
    0x0D : 0x401f
    0x0E : 0x0000
    0x0F : 0x0000
    0x10 : 0x0205
    0x11 : 0x010b
    0x12 : 0xe400
    0x13 : 0x0000
    0x14 : 0x0000
    0x15 : 0x0000
    0x16 : 0x0100
    0x17 : 0x0000
    0x18 : 0x1a25
    0x19 : 0x0c00
    0x1A : 0x0000
    0x1B : 0x0000
    0x1C : 0x0000
    0x1D : 0x0000
    0x1E : 0x0000
    0x1F : 0x0000
    0x0450: 0x2610
    0x0451: 0x0000
    0x045D: 0x62c0

    Another issue, 

    Do you have the link up time test result in the DP83TC812EVM-MC?

    The OPEN Alliance Automotive Ethernet ECU Test requirement as below:

    Below is test from DP83TC812EVM-MC:

    It has exceeded 100ms.

    Best Regards!

  • Hi Jingkun,

    Can you probe LED1 as well? This should also indicate link activity, I want to see if it is similar to the LED0 waveform you are seeing. 

    Below is read back register's value:

    Thank you providing this. The registers look as expected and the strap register 0x45D says you are correctly strapped into master mode. 

    Do you have the link up time test result in the DP83TC812EVM-MC?

    The OPEN Alliance Automotive Ethernet ECU Test requirement as below:

    Yes, we have an Interopability repot available from C&S. We typically give this out to ur customers with NDA, can you reach out to your local TI Field Representative for this?

    Below is test from DP83TC812EVM-MC:

    It has exceeded 100ms.

    This LED0 waveform does not look correct. To debug, can you (1) measure LED1 and (2) try depopulating the pull up resistor on LED0 and measuring the waveform again, and (3) measuring TRD_P and TRD_M with a differential probe?

    While LED0 can be used to indicate link status, it should not be used to measure the link up time because there is some delay.

    The Open Alliance Test house has a more precise test setup to measure the time that is a bit difficult to replicate. However, you can get an estimate by using a differential probe to measure across TRD_M and TRD_P.

    This is what my waveform look like:

    Best regards,

    Melissa

  • Hello Melissa,

    This LED0 waveform does not look correct. To debug, can you

    (1) measure LED1 

    ---> Add LED1 in the waveform

    (2) try depopulating the pull up resistor on LED0 and measuring the waveform again

    ---> It was used DP83TC812EVM-MC for testing. It has the pull up resistor.

    (3) measuring TRD_P and TRD_M with a differential probe?

    ---> OK.

    Below is test result:

    I don't know how to judge the link up time from the TRD_P/M.

    Could you add the comment in the waveform?

    Best Regards!

  • Hi Jingkun,

    Thanks for providing this information! 

    It looks like from the TRD_P/TRD_M waveform it is linking up twice. 

    In the DP83TC812MC EVM and in the SW drivers we provide, there is an Open Alliance Compliance initialization sequence, which restarts the PHY (0x1F=0x4000) and restarts the link up process, so it is expected. 

    I have circled link DOWN in blue, link UP in purple, and link training/link up in red. Link up timer begins with the sending of PAM3 idle signals (in red).

    For the LED0 waveform, it looks like polairty is being inverted to active LOW. Can you 

    (1) Confirm that no HW/SW changes have been made to the EVM. Did you replace the 812 with 814?

    (2) provide a picture of your DP83TC812MC-EVM? I want to check strap settings.

    (3) Try writing 0x451[0]=1 to invert the polarity to see if that fixes the polarity

    Best regards,

    Melissa

  • Hello Melissa,

    (1) Confirm that no HW/SW changes have been made to the EVM. Did you replace the 812 with 814?

    ---> It doesn't have any changes in the EVM.  We didn't replace the 812 with 814.

    (2) provide a picture of your DP83TC812MC-EVM? I want to check strap settings.

    ---> Please check below picture:

    (3) Try writing 0x451[0]=1 to invert the polarity to see if that fixes the polarity

    ---> The polarity inverted when writing 0x451[0]=1.  We find that LED_0 is active low when it is in master mode. And LED_0 is active high when it is in slave mode.  We don't do any configuration.  Is this consistent with TI's design expectations?

    Best Regards!

  • Hi Jingkun,

    Apologies for the confusion. 

    If LED0 is pulled HIGH (strapped into master mode), it will be Active LOW. 

    If LED0 is NC or pulled LOW, it will be Active HIGH.

    If you leave LED0 NC or pulled LOW, it will still be Active HIGH even if you program the PHY to Master Mode via register writes.

    Best regards,

    Melissa

  • Hello Melissa,

    I got the link up time test report.

    Below questions, could you help to confirm again?

    1. The DUT’s PHY configuration must be finished within 20ms after reset.  Do you give us the configuration document?

    2. DUT shall wait until the PHY indicates an active link and stop timer t0.  How to get the info that PHY indicates an active link?  Read the register 0x001[2]?

    Best Regards!

  • Hi Jingkun,

    1. The DUT’s PHY configuration must be finished within 20ms after reset.  Do you give us the configuration document?

    This is provided in the test report, section 9.3 Configuration Script.

    The registers used for configuration are also found here in section 3: https://www.ti.com/lit/an/snla389b/snla389b.pdf?ts=1719362666393 

    2. DUT shall wait until the PHY indicates an active link and stop timer t0.  How to get the info that PHY indicates an active link?  Read the register 0x001[2]?

    There is some latency and delay in reading 0x001[2], I don't believe this will work. I will need to check how this is measured and get back to you by the end of the week.

    Is there a particular reason you want to measure t0? Are you testing a link partner that is not part of our test report?

    Best regards,

    Melissa

  • Hello Melissa,

    Now, we are testing the link up time. But the test result is more than 100ms.

    We recorded the link up time is from reset release to reading the register 0x001[2].

    We test the link partner :  master is DP83TC814SRHARQ1 and the slave is DP83TC814SRHARQ1.

    So we want to know TI using which signal as the indication an active link.

    Best Regards!

  • Hi Jingkun,

    If it is your custom board, can you (1) check that you are programming the Open Alliance init script and (2) LED and TRD_P/TRD_M waveforms?

    The Init script can be found here for Master and Slave modes in section 3: https://www.ti.com/lit/an/snla389b/snla389b.pdf?ts=1719511922160 

    From the waveforms you provided, the link up time is <100ms on the TI EVMs. 

    Best regards,

    Melissa

  • Hello Melissa,

    • Are you measuring link up time on your custom board?     
      --> Yes. We are measuring link up time on our board.
    • Are you using our linux or RTOS driver? (https://github.com/TexasInstruments/ti-ethernet-software/tree/main ) 
      --> Our SW team is confirming.
    •  (2) LED and TRD_P/TRD_M waveforms
    • From the waveforms you provided, the link up time is <100ms on the TI EVMs.
      --->It has two red box, it means that it has twice link. Does TI use the time that RESET signal high to the first red box for link up time?

            If it measures to the second red box time, it also is more than 100ms.

    1. There is some latency and delay in reading 0x001[2], I don't believe this will work. I will need to check how this is measured and get back to you by the end of the week.

    --> Could you give us the confirm result that how this is measured?

    2. About the test report, it has some questions, please help to confirm:

    2-1) About the Step 1, does the soft/hard reset mean the register 0x1F[15-14]? Or the pin 3 RESET_N?

       

    2-2) About the Step 3, the t0 is after finished configuration. Doesn't the link up time include the time spent on configuration?

    Best Regards!

  • Hi Jingkun,

    It seems like the 814s on your custom board is linking up within the correct time. I do not see a problem here from the waveforms you provided. 

    ...

    --->It has two red box, it means that it has twice link. Does TI use the time that RESET signal high to the first red box for link up time?
          If it measures to the second red box time, it also is more than 100ms.

    The linkup time is only the 2nd red box, not the 1st red box.

    2-1) About the Step 1, does the soft/hard reset mean the register 0x1F[15-14]? Or the pin 3 RESET_N?

       

    1. There is some latency and delay in reading 0x001[2], I don't believe this will work. I will need to check how this is measured and get back to you by the end of the week.

    --> Could you give us the confirm result that how this is measured?

    C&S (official test house) uses register 0x133. However, they some advanced automated setup that measures this with only a microsecond delay. It is hard to replicate. We typically measure at TI by looking at the TRD_P and TRD_M waveforms which provide a good estimate.

    2-1) About the Step 1, does the soft/hard reset mean the register 0x1F[15-14]? Or the pin 3 RESET_N?

       

    Hard reset is 0x1F=0x8000

    Soft reset is 0x1F=0x4000

    2-2) About the Step 3, the t0 is after finished configuration. Doesn't the link up time include the time spent on configuration?

    For T0, they start the timer after reset in the software and stop the timer after config is done. The requirement for this is 20ms. However, C&S has a advanced automated setup with microsecond delay to measure. It is hard to replicate.

    The passing report we forwarded to you shows we have already passed this spec before, since we have passed IOP21. The config time is unrelated to the link partner. 

    Best regards,

    Melissa

  • Hello Melissa,

    --->It has two red box, it means that it has twice link. Does TI use the time that RESET signal high to the first red box for link up time?
          If it measures to the second red box time, it also is more than 100ms.

    The linkup time is only the 2nd red box, not the 1st red box.

    --> The time is about 556ms from Pin_3(RESET_N) high to the 2nd red box. It has exceeded 100ms.

    So we don't know the resetting PHY means that Pin_3 (RESET_N) changes from low to high, or it means resetting the register.

    If the reset PHY means Pin_3 (RESET_N) changes from low to high, the link up time of demo also exceeded the SPEC requirement.

    Are you base in China? If yes, could you have a talk via phone?

    Below is my phone number:18030086702.

    Best Regards!

  • Hi Jingkun,

    Can you confirm what driver is being used and provide the driver file aswell?

    --> The time is about 556ms from Pin_3(RESET_N) high to the 2nd red box. It has exceeded 100ms.

    It seems there has been some confusion, I was talking about this image where I have drawn red boxes, not the one you've showed above:

    The link up time in this green waveform is the 2nd red box.

    In the new image below, the link up time is the yellow box I have drawn below. 

    On our EVM it should be measured from the register write, not the pin. For future reference hard reset is 0x1F=0x8000 and soft reset is 0x1F=0x4000.

    For your board, I need to confirm in the software driver what register writes are being done after reset. 

    If there is still some confusion we can setup a meeting, please reach out to your local Field Representative to set this up. I am based in the PST Time Zone. 

    Best regards,

    Melissa

  • Hello Melissa: 

    It seems there has been some confusion, I was talking about this image where I have drawn red boxes, not the one you've showed above:

    --> Sorry, I used the wrong picture. Below is demo test result:

    The time is about 556ms from Pin_3(RESET_N) high to the 2nd red box. It has exceeded 100ms.

    On our EVM it should be measured from the register write, not the pin. For future reference hard reset is 0x1F=0x8000 and soft reset is 0x1F=0x4000.

    --> It means that the link up time is from register 0x1F=0x8000 or 0x1F=0x4000 to 0x133[12] =1.  Is it right?

    Best Regards!