DS90UB933-Q1: Ask some question about the application

Hello Jack,

Jack Li said:

1.The UB913, UB913A, and the UB933 are all pin-to-pin compatible, I wonder if they can be used as a direct replacement in an existing design when set 10bit mode, I mean use same PCB, same software and same components， just solder different Ser devices;

913A and 933 are direct replacement. 913 is pin-to-pin but supports only STP, no coax.

Jack Li said:

For UB933-UB934 application, I think they support  BT.656 8-bit and BT.601 16-bit, do they support BT.1120?

These devices did not implement circuitry to extract the embedded hsync/vsync values. If hsync/vsync have separate connections, then yes.

Jack Li said:

3. My customer system power up sequence doesn't meet with the requirement of datasheet, VDD_n power up before VDDIO, here is their initial code, please check if it's OK:

The above code will help if t3 (VDDn to PDB delay) is not maintained. But if your VDDn comes up later than VDDIO, that code will not help. They need to change the hardware design.

Jack Li said:

Besides, do we have other ways to initial if the power up sequence doesn't meet with the requirement of datasheet?

We have not tested other methods of initializations if power-up sequence is not met, but if they apply PDB reset, that might help. During this, PDB pin must stay low for at least 5 ms before high again. Also, during this reset time GPIO2 must held low.

Jack Li said:

For SOC-UB933-UB962 application, if SOC output wrong data to UB933， is there a register to indicate this error?

What error exactly do you want to indicate? And what do you mean by wrong data?

Hi Hamzeh,

Thanks for your reply~

As for question4, I mean when the SOC doesn't output the video normally, is there a register in UB934 to indicate this error?

Best Regards,

Jack

Hi Hamzeh,

Thanks for your reply, as we can see in the UB933 datasheet, T3 needs to be less than 16ms, but my customer's design doesn't meet with requirement, the T3 in their design is about 35ms. They wonder what will happen if  T3>16ms, is there any risk if they don't reset it with IIC configuration?

By the way, there is no requirement in UB933 Rev.A datasheet:

Best Regards,

Jack

Hi Hamzeh,

If my customer meet with this 1ppm start-up issue, do we have any way to recover it, like pull  down PDB pin or write IIC configuration, thanks!

Best Regards,

Jack

Hi Hamzeh,

My customer do have this problem that the T3 is 35ms, they have some concern about it, please help to clarify them, thanks in advance~

1. This project is PV and couldn't change the hardware, they wonder if this 1ppm start-up issue will be recover by restart system(with same sequence that T3=35ms), is there a risk to damage the UB933 device？

2. What's the risk if VDD_n power on before VDDIO, which means that T1<0, please tell us what may happen and the issue rate. Do we have any other ways to reduce this risk except changing the hardware?

Best Regards,

Jack

Hi Hamzeh,

Thanks for your reply~

As said before, my customer couldn't change the hardware anymore, so they care about the risk:

Hamzeh Jaradat said:

not following the right sequence will lead to unexpected behavior because this may not power on the device properly.

1. If UB933 T1 power up timing isn't satisfied, what may take place, and how many PPM the risk will be ;
2. If UB933 T1 power up timing isn't satisfied, does no output phenomenon will appear? If yes, do we have any way to monitor it? And do we have any ways to recover it, like pull down PDB or IIC configuration?

Best Regards,

Jack

Hi Hamzeh,

Hamzeh Jaradat said:

If the issue occurs, there will be no output from the serializer forward channel. Hence, there is no deserializer lock will be observed

Estimated risk ~1ppm

Thanks for your reply, just double check, UB933 T1 power up timing isn't satisfied means that VDD_n power up before VDDIO, is the risk ~1ppm?

Best Regards,

Jack

Hi Logan and Hamzeh,

As said before, my customer couldn't change the hardware anymore, so they care about the risk:

1. If UB933 T1 power up timing isn't satisfied, what may take place, and how many PPM the risk will be ;
2. If UB933 T1 power up timing isn't satisfied, does no output phenomenon will appear? If yes, do we have any way to monitor it? And do we have any ways to recover it, like pull down PDB or IIC configuration?

Thanks for your kindly reply~

Best Regards,

Jack