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[FAQ] SN65DPHY440SS: What is the design constraint for DPHY440 lane 0 when using in a MIPI CSI design?

David (ASIC) Liu
Guru**** 150755 points
Part Number: SN65DPHY440SS
Other Parts Discussed in Thread: SN75DPHY440SS

Tool/software:

I'm utilizing the SN75DPHY440SS in 4 lane configuration with default configuration parameters, sourced by a CSI-2 source.  Lanes 1, 2, and 3 are correctly driven and re-drive both LP and HS signals.  

Lane 0 is driven by the same source but fails to pass HS data (oddly, LP data is being passed correctly).

This "shouldn't" matter, but we are NOT abiding by lane ordering (i.e. MIPI lane 4 passes through DA0P/DA0N) - per the datasheet, that's acceptable.

Source receiver and termination is identical for each lane.

Any thoughts or similar experiences?

  • 0
    TI__Guru**** 150755 points

    Hi,

    The DPHY440 is a one to four lane and clock MIPI DPHY re-timer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at data rates of up to 1.5 Gbps. 

    The MIPI DSI specification defines bidirectional communication between the host and peripheral. When a response is needed by the peripheral, the response is returned using LP signaling from DB0P/N to DA0P/N. The DPHY440 only supports this communication over lane 0 (DB0P/N to DA0P/N).

    Unlike DSI, CSI-2 does not have a back channel path. But when using DPHY440 in a MIPI CSI-2 design, special attention must be paid to lane 0. With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX.  If DB0P/N LP TX is connected to a HS RX, then LP signaling will not be able to reach the LP11 levels and which will cause the DPHY440 to not enable HS data path on Lane0.

    Below is a workaround to disable LP and enable HS path on lane 0 only. Please note with LP being disabled, the source must send only HS data. 

    Enable HS path for Lane 0 only:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path

    Write Register 0x51 with 8’h01 //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h01  //Override enable for HS RX path

    Write Register 0x71 with 8’h01  // HS RX path enabled.


    Bit 0 is lane 0

    Thanks

    David