Tool/software:
Hi TI Team.
We are using AM6254 and DP83867 in compute module.
Here, We observed timing related issue in RGMII interface. TXCLK and TXD0 data having more rise and fall time and does not able to achieve required Setup and Hold time of 1nS.
Refer attached image. Setup time is around 322ps ( Measured between VIL of dataline to Centre of clock).
We had EVM with us as well (E3A version). We tried measuring signals with that board and found good signal with it. We able to achieve 1.2nS setup and hold time here.
Is there anything related to drive capacity control here? Overall impennate observed similar in our design and EVM board.
Can you advise further steps to troubleshoot this issue?
