Tool/software:
Hi Team,
When the customer read Register 0x006F, Bit[8] = 1.
This bit is Reserved bit and the default is "0", Read Only.
- Is there a possibility that this bit will be asserted to "1" when shipped?
- Also, is there a possibility that the other reserved bit(Bit[7], [6:4] and so on) will be asserted to "1" when shipped?
- Will this have any effect on the works of the PHY?
Device: PAPT
Best Regards,
Hi Atsushi,
This is a good question. I checked a known good board with the RGZ version of the 867 and also read Reg 0x6F, Bit[8]=1. This part is functional and this shouldn't affect the customer's board. To confirm the other reserved bits I would need to check other boards and discuss with our design team, which would take time.
Bits 6:4 are the same as the RGZ, they are what RGMII TX_CLK delay is added, which is controlled by the strap settings.
Regards,
Alvaro
