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TCAN1146-Q1: Bus Fault Questions

Muwei Zheng
Intellectual 1060 points
Part Number: TCAN1146-Q1
Other Parts Discussed in Thread: TCAN1043-Q1, , TCAN1043, TCAN1145EVM

Tool/software:

Hi team,

Could you help take a look at below questions from customer about TCAN1146-Q1 and TCAN1043-Q1?

TCAN1146

1. How do we clear the bus fault?

- Datasheet says Bus Fault ( CANH & CANL -> SCG, SCB; Short b/w CANH and CANL etc.,) would be detected if the fault present during the four dominant to recessive transition with each dominant bit being ≥ 2 µs.

I understand that bus Fault would store in register 8'h54. I would like to understand, how do we clear this fault in TCAN1146?

( In case of TCAN1043A, it says that Bus fault flag cleared, in normal mode, if no CAN bus fault is detected for four consecutive dominant-to-recessive transitions on the TXD pin or leaving the Normal mode)

2. Range of differential resistance load to detect Bus fault

- Is the bus fault (CANH Shorted to VBAT, CANH Shorted to GND, CANL Shorted to VBAT, CANL Shorted to GND, CANH Shorted to VCC, CANL Shorted to VCC) depends on the differential CAN Bus resistance?

  (In case of TCAN1043, bus fault circuitry able to detect the mentioned bus fault with the Bus differential resistance b/w 45 to 70 ohm )

3. Do we have EVM for TCAN1146? In TI website I could see only for TCAN1043 not for TCAN1146

TCAN1043

1. After initial power ON, nFault stays “LOW” but, it still “LOW” even the mode changed to Normal. Is this expected?

( nFault going to “HIGH” after a data being transmitted on the Bus or upon leaving the normal mode )

Thank you,

Muwei Zheng

  • 0
    TI__Intellectual 1060 points

    Hello team, would you provide any feedback here?

  • 0
    TI__Guru 50165 points

    Hi Muwei,

    Muwei Zheng said:
    1. How do we clear the bus fault?

    Any clearable interrupt bit in the interrupt status registers (h51 - h54) can be cleared by writing a 1 to the corresponding bit position. For example, to clear the "CANL shorted to Vbat" interrupt, a write to INT_CANBUS (h54) of value 0x01 can be done.

    Muwei Zheng said:
    2. Range of differential resistance load to detect Bus fault

    The fault detection circuit is current sensing based, so the detection mechanism will be sensitive to different resistance values in the short. Because this measurement method is also sensitive to other conditions (temperature, dominant bit timing, and other bus characteristics), we do not specify a given resistance value for when positive faults will be detected. 

    Muwei Zheng said:
    3. Do we have EVM for TCAN1146? In TI website I could see only for TCAN1043 not for TCAN1146

    The TCAN1145EVM may be used for the TCAN1146.

    Muwei Zheng said:
    1. After initial power ON, nFault stays “LOW” but, it still “LOW” even the mode changed to Normal. Is this expected?

    Yes. nFAULT is also used to indicate wake events and wake sources. Please reference Table 8-1 for the full description of indicators for this pin. 

    Let me know if you have any more questions. 

    Regards, 
    Eric Schott

  • 0 in reply to Eric Schott1
    TI__Intellectual 1060 points

    Hi Eric,

    Thank you for your response. I have some follow up questions from customer below:

    Eric Schott1 said:
    Any clearable interrupt bit in the interrupt status registers (h51 - h54) can be cleared by writing a 1 to the corresponding bit position. For example, to clear the "CANL shorted to Vbat" interrupt, a write to INT_CANBUS (h54) of value 0x01 can be done.

    1A. sorry for the basic question. Is the Bus Failure would set the interrupt register.bit to “1” or “0” ? I thought, If any Bus failure happens, that would set the interrupt register’s corresponding bit to “1”.  For example, If “CANL shorted to Vbat” happens, I thought that failure would set h54.bit0 to “1”. Is this wrong understanding?

           In case my understanding is correct , the failure would sets the interrupt register bit to “1” then we must write back to “0” to clear it. Is this right understanding? Or will it work other way around?

    1B. I understand that writing “1” / “0”  (depends on answer from 1A) back to corresponding bit position will clear the bus fault…But, as like TCAN1043, can we also expect that the BUS fault would be cleared automatically “ if we leave the normal mode OR if no CAN bus fault is detected for four consecutive dominant-to-recessive transitions on the TXD pin”?

    Eric Schott1 said:
    The fault detection circuit is current sensing based, so the detection mechanism will be sensitive to different resistance values in the short. Because this measurement method is also sensitive to other conditions (temperature, dominant bit timing, and other bus characteristics), we do not specify a given resistance value for when positive faults will be detected. 

    2A. our CAN node termination ( one node) 116ohm 0.5% ( and so the other end node also)  . Can I expect the Bus fault would be detected with this termination (ECU internal amb 105deg to -40deg)?

           My date bit rate expected to be 2.5M, 3.3M, 5M

  • 0 in reply to Muwei Zheng
    TI__Guru 65862 points

    Muwei,

    Muwei Zheng said:

    1A. sorry for the basic question. Is the Bus Failure would set the interrupt register.bit to “1” or “0” ? I thought, If any Bus failure happens, that would set the interrupt register’s corresponding bit to “1”.  For example, If “CANL shorted to Vbat” happens, I thought that failure would set h54.bit0 to “1”. Is this wrong understanding?

           In case my understanding is correct , the failure would sets the interrupt register bit to “1” then we must write back to “0” to clear it. Is this right understanding? Or will it work other way around?

    Your understanding is correct, if the interrupt from a bus fault is detected, that specific interrupt will be set to 1 in the registers. To clear the interrupt, you write a 1 to that specific bit and it will clear to 0 unless the fault is still present.

    Muwei Zheng said:
    1B. I understand that writing “1” / “0”  (depends on answer from 1A) back to corresponding bit position will clear the bus fault…But, as like TCAN1043, can we also expect that the BUS fault would be cleared automatically “ if we leave the normal mode OR if no CAN bus fault is detected for four consecutive dominant-to-recessive transitions on the TXD pin”?

    No, the interrupt will remain latched until the fault is no longer present and the interrupt is cleared by writing a 1 to the specific bit.

    Muwei Zheng said:

    2A. our CAN node termination ( one node) 116ohm 0.5% ( and so the other end node also)  . Can I expect the Bus fault would be detected with this termination (ECU internal amb 105deg to -40deg)?

           My date bit rate expected to be 2.5M, 3.3M, 5M

    The termination resistance is within range, but the CAN bus fault detection circuitry works best when the overall bus impedance is as close to 60 ohms as possible. 

    The CAN bus fault detection only works up to 1Mbps, so when operating at data rates greater than 1Mbps CAN bus fault detection will not work.

    Regards,

    Eric Hackett