TCAN4550: SCH REVIEW

Hi Jingguo,

I have reviewed the schematic and I have the following comments:

- The nWKRQ pin should not be connected to GND because this will be driven to a 3.6V voltage during Sleep Mode and this will result in a large current flow with a direct connection to GND.  If this pin is going to be unused in the system, it should be left unconnected.

- The RST pin is "Active High" and should be held "LOW" for normal operation.  The RST pin is also being pulled to +3.3V instead of the +5V-CAN rail being supplied to VIO and for all of the other digital IO signals.  I don't know if this is an intentional decision.

- The VSUP supply voltage needs to be greater than 6V due to the internal 5V LDO.  Using the +5V-CAN voltage will be too low and the device will be held in an under-voltage protected mode.  The VSUP should be connected to the +12V supply rail.

- The SPI Chip Select pin (nCS) must be connected to the processor with the rest of the SPI signals.  It must transition from High-to-Low at the beginning of the SPI read/write transaction, remain Low for the duration of the data, and then transition from Low-to-High at the end of the transaction.  If the nCS signal does not transition, then SPI communication will not work.  Please refer to the SPI programming section of the datasheet.

- The Interrupt pin (nINT) is an open-drain architecture that requires a pull-up resistor to the VIO supply rail.

-  It is recommended to include a series resistor between the OSC1 pin and the crystal to help optimize the circuit for stable performance.  A 0-ohm resistor can be used and adjusted to a different value later if needed.  Please see the TCAN455x Clock Optimization and Design Guidelines Application Note (Link)

- The crystal load capacitors are connected to a different GND than the rest of the device.

Regards,

Jonathan