TLK10081: Asymmetrical bitrate passing throught the mux

Hi Guillaume,

I'm not very familiar with how download and upload speeds translate to your system block diagram. Does download speed correspond with one direction of transmission, while upload speed corresponds with the other direction? If this is correct, can you clarify which direction is experiencing packet loss and if there are any differences between the 2 boards?

I also reviewed your register configuration and I have a few questions.

1. Did you follow some guide or document to determine this register write sequence?
2. I see that you enable lane marker generation (0x17 = 0x0ABC), then disable lane marker generation 5 seconds later (0x17 = 0x2BC). Can you explain the reasoning behind this sequence?
3. What is the reasoning for reading registers 0x02 and 0x06 at the beginning and end of the sequence?

Best,

Lucas

Hi Lucas,

Thanks for your reply,

There is an update version of my block diagram to complete the understanding of the situation :

I experience packet loss in both directions. There is no difference between the 2 boards (same schematic, same layout)

Regarding register configuration :

1. I followed the exact configuration setup that you have recommanded here (e2e.ti.com/.../tlk10081-8-gbps-ethernet-over-fiber-bridge)

    0x1=0x0302
    0x2=0x831b
    0x6=0x8114
    0x1c=0x002c
    0x1d=0x002c
    0x17=0x0abc
    wait 1s, write 0x17=0x2bc

2. Same answer as above, exept wait is 5 s and not 1 s

3. Reading registers 0x02 and 0x06 are just here to check the configuration

Kind regard,

Guillaume

Hi Guillaume,

Thank you for the clarification. While the system is in operation, can you readback registers 0x0F, 0x13, and 0x14 on both TLK devices, both channels a few times and share the values?

Best,

Lucas

Hi Lucas,

First time I read in registers (after turning on the system ON) I had the following results :

0x0F : 0x4134

0x13 :0x4E01

0x14 :0x0001

Then, when I tried to read again (many times), I had : 

0x0F : 0x1D27

0x13 :0x6E01

0x14 :0x0001

Value of registers are the same for both TLK10081

Thanks for the support,

Guillaume

Hi Guillaume,

Thank you for reading and sharing. I see the following errors:

• 0x0F[8]=1: HS_DECODE_INVALID
• 0x0F[5]=1: BIT_LM_FAIL
• 0x0F[4]=0: BIT_LM_DONE is de-asserted
• 0x13[11]=1: LS_INVALID_DECODE
• 0x13[10]=1: LS_LOS
• 0x13[9]=1: LS_RXLOS_DETECT_LH
• 0x13[8]=0: LS_CH_SYNC_STATUS is de-asserted
• 0x13[0]=1: LS_RX_FIFO_OVERFLOW
• 0x14[0]=1: HS_RX0_FIFO_OVERFLOW

I believe each of the LS errors shown correspond to one low-speed lane, likely lane 0. Can you iterate through each value of 0x06[14:12] to access each LS lane and read 0x13 a few times after each change? Can you check on both TLK10081 units and share the values you see?

Best,

Lucas