Clock and Data Question for LMH0051

The LMH0051 is intended as a receiver for data which is formatted according to the SMPTE 259  and SMPTE 292 standards.   The serial input to the device should match the SMPTE standard - either as a 270Mbps stream or a 1.5Gbps stream, the output of the device is a 5 bit parallel LVDS bus, and a clock.  The default is for the clock to be a DDR clock, so that the 5 bit data bus transitions after each clock transition - this means that when receiving 270Mbps data, the clock is at a frequency of 27MHz. which is what is shown in the upper pair of traces.   There is an option for the clock to be run at 1/2 of this rate - or a frequency of 13.5MHz, in which case the data transitions four times during each clock cycle.   This mode is mostly used when the device is being used to receive higher data rates than the standard definition data rate.

In most applications, the LMH0051 output goes to an FPGA which decodes the data and will provide you with a 13.5MHz, 20 bit wide data stream.   The IP to perform this function is available through the TI sales channel, and is free of charge.   We provide source code in both Verilog and VHDL, and example versions for both Xilinx and Altera FPGAs.

We offer the IP in source code, and have example versions for Altera and Xilinx but we do not have a Lattice example.   It should not be difficult for a customer to adapt the existing IP to a Lattice FPGA if they wish to do so.