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Clock and Data Question for LMH0051

Jacob Ontiveros
Expert 6280 points
Other Parts Discussed in Thread: LMH0051

Hi Team,

I am assisting a customer who is using one our SVA parts. The customer is using a LMH0051 Deserializer with an SD SDI Input. A clock of 27 MHz and 20 bits of data at 54 MHz is received from the LMH0051. If this is its correct function are ten of the bits valid bits?

It is my understanding that register 28H can be changed to modify the clock and data frequencies. When the clock frequency is lowered by a factor of two (Address 28 bit 6 is set to 0), the Data frequency still remains 54 MHz. Does modifying this register only change the clock frequency?

The customer took o-scope shots of the data and clk.

Cyan: Clock

Magenta: Data

This waveform shows the clock operating at 27 MHz.

This waveform shows the clock operating at 13.5 MHz.

Is there a place where I can find additional support on this device or devices like this one? Any help is greatly appreciated.

Thanks,

Jacob O.

  • 0
    TI__Genius 13475 points

    The LMH0051 is intended as a receiver for data which is formatted according to the SMPTE 259  and SMPTE 292 standards.   The serial input to the device should match the SMPTE standard - either as a 270Mbps stream or a 1.5Gbps stream, the output of the device is a 5 bit parallel LVDS bus, and a clock.  The default is for the clock to be a DDR clock, so that the 5 bit data bus transitions after each clock transition - this means that when receiving 270Mbps data, the clock is at a frequency of 27MHz. which is what is shown in the upper pair of traces.   There is an option for the clock to be run at 1/2 of this rate - or a frequency of 13.5MHz, in which case the data transitions four times during each clock cycle.   This mode is mostly used when the device is being used to receive higher data rates than the standard definition data rate.

    In most applications, the LMH0051 output goes to an FPGA which decodes the data and will provide you with a 13.5MHz, 20 bit wide data stream.   The IP to perform this function is available through the TI sales channel, and is free of charge.   We provide source code in both Verilog and VHDL, and example versions for both Xilinx and Altera FPGAs.

  • 0 in reply to Mark Sauerwald88474
    TI__Expert 6280 points

    Thanks Mark for the quick response.

    Thanks Again,

    Jacob

  • 0 in reply to Jacob Ontiveros
    TI__Expert 6280 points

    Hi Mark,

    Sorry to bother you again, but is there a Lattice version of the IP?

    Thanks,

    Jacob

  • 0 in reply to Jacob Ontiveros
    TI__Genius 13475 points

    We offer the IP in source code, and have example versions for Altera and Xilinx but we do not have a Lattice example.   It should not be difficult for a customer to adapt the existing IP to a Lattice FPGA if they wish to do so.

  • 0 in reply to Mark Sauerwald88474
    TI__Expert 6280 points

    Thanks again for the help Mark.