DP83867CR: MDI signal length layout constraints, RGMII RX drive strength, MAC I/O output impedance

Part Number: DP83867CR

Tool/software:

We are using the 1G DP83867CR ethernet PHY and have a few questions.

We have a layout constraint that requires the transformer and external signal launches to be located 12-18 inches away from the microcontroller.  The DP83867 datasheet layout guidelines specify a maximum of 6 inches for the RGMII interface.  Can we extend the MDI side signals up to 12 inches as long as we adhere to impedance control and length matching rules?

What is the drive strength of the RGMII RX signals?  The only clue in the datasheet is the Ioh and Iol of 4mA for Voh and Vol specs.

The output impedance of MAC I/Os are trimmed internally to 50 ohms per the datasheet page 101.  This means to me that we do not need to source terminate if we control our trace impedance to 50 ohms, correct?

Thanks,

Brian

  • Hi Brian,

    In terms of your questions:

    1) While non-ideal, I would rather we minimize the MDI as much as possible than the MII. This is due to the speed and amplitude of the MDI vs MII, where the MDI is much more sensitive to parasitics.

    2) For drive strength, we encourage you to simulate with our IBIS files to ensure that the SI is accounted for. From PHY standpoint, so long as on the TX (input) lines, that the setup/hold and VIH/L parameters are met, the MII should work.

    3) This is correct. You may also adjust this via register within the PHY to correct for any over/undershoot.

    Sincerely,

    Gerome

  • Hi Gerome,

    Some additional information:

    • The worst case trace differential is 237 mils on the RGMII interface which is ~42ps. Do we have a recommended max difference when using a 25MHz reference clock with a 1.8V interface voltage?  The total length is 18 inches, and they routed them as a striplines.
    • Additionally, attached is a scope capture of RXCLK(magenta) and RXD0 (yellow). I am a bit concerned that RXD0 doesn't look to fully settle on the logic high bit level. They are seeing 1.5ns rise time which is about 18% of the clock period worst case, and they were able to get communication to work by adjusting RGMII_RX_DELAY_CTRL in the PHY from 2.25ns (0x8) to 2.75ns (0xa).  They said the slower rise times were eating into the setup time making it marginal for just some of our boards.  Adjusting this value helped and did not seem to cause any hold time violations.  They left it running overnight without any ping timeouts. Any concerns here?

    Thanks,

    John

  • Hi John,

    Our layout app note provides our best recommendations for layout. I would imagine that VDDIO level is independent of trace length recommendations. I can understand the concern that the levels don't fully stabilize, but the VIH for a 3.3V (assumed VDDIO) signal is 1.7V which this does clear. I would think that the functional test that customer ran should alleviate concerns of any issues.

    Sincerely,

    Gerome