Original question:
Part Number: AM62L
Other Parts Discussed in Thread: CSD, TMDS62LEVM
Hello Team ,
While checking the eMMC boot we are facing the issue in some boards
I have attached the log , May i know the reason behind the failure.
Bootissue.log
Regards,
Ninad
Hello Ninad,
The EXT_CSD (Card Specific Data register ) is available at the eMMC memory side. Generally, you should be able to write to the EXT_CSD writable bitfields over the eMMC HW interface. Please check the documentation of your eMMC flash memory on the related bitfields attributes - i.e. are they writable, details, etc.
Here is an excerpt from an EXT_CSD related example thread that shows that an eMMC Flash memory.EXT_CSD register bit is writable:
Also here are EXT_CSD related excerpts of the below eMMC related FAQ: FAQ - eMMC Memory Interface :
Thanks
Kind Regards
Anastas Yordanov
Is it compulsory to write that "mmc extcsd" for eMMC booting ?
Can U tell if this is EVM board value?
Hi Ninad,
Regarding the hardware guidance I initially provided to you :
"1. I think that the correct pull-up and pull-down resistors are mounted (I think you can keep the external 10k pulls and no need to replace pull-ups on data and cmd I/Os by 47k). Another question comes - do you have any placeholders for series termination resistors located as close as possible to the eMMC signal source pins ( signal drivers). A good approach is to start tests with 0R series resistor values and probing the eMMC_CLK, eMMC_DAT0-eMMC_DAT7, eMMC_CMD lines with scope to evaluate the signal integrity. If overshoot / undershoot present, you can gradually increase series resistance to 10R, 22R, 33R until signal shape is improved and keeping the rise and fall times still acceptable."
I have to correct myself as follows:
You were correct, it is better to use eMMC_CMD and eMMC_DAT0 external pull-up resistor values of 47 kOhms, because 10 kOhms is the minimal JEDEC eMMC recommended pull-up resistance value, and to avoid any negative % tollerance issues.
This is as per design note in the Sheet 25 of the: sprcal9\TMDS62LEVM Design File Package Altium (Rev. B)\PROC180\PROC181E1_1\1_SCHEMATIC\3_PDF_Intelligent\PROC181E1-1_S_SCH_With_Design_Updates..Notes_V1.0.pdf
For the eMMC_DAT1 - eMMC_DAT7 lines please make sure to enable the internal pull-up resistors. Once again, have a pull down 10 kOhm resistor attached closer to the eMMC_CLK input of the eMMC memory, and attach a 10 kOhm pull-down resistor closer to the eMMC_DS input of the AM62L processor.
According to the TMDS64LEVM schematic, and schematic review checklist, you actually need to have a placeholder for series termination resistor only for the eMMC_CLK clock line, as close as possible to the signal source (the AM62L eMMC_CLK output pin). You should start with a 0R resistor and gradually increase the value ( 3R3, 4R7,10R, 22R, 33R,..) or other standardized low-resistance values until clock has an ignorable ringing effect (overshoot / undershoot) in the plateau area. At the same time the recommended for highest frequency (200MHz) rise and fall times shall be respected, not allowing a higher series resistance value to increase the eMMC clock rise/fall time above the allowed maximal values.
Below is the excerpt of the Section, MMC0 - eMMC (Embedded Multi-Media Card) Interface of the AM62L Schematic Review Checklist
Please provide the details regarding the used measurement equipment, as far as the requested details can be disclosed here.
Thank you
Regards
Anastas Yordanov
What is the eMMC_CLK frequency at which A53 SPL reads the u-boot.img from eMMC memory to RAM ? Is it 25 MHz or higher ?
By default, the eMMC is initialized in the HS200 so it is 200MHz.
Successfull boot
On comparing the non-working and the working logs, the first difference comes at the following place
This is CMD18 initiated for reading the u-boot.img. This command fails with the communication error (-70) in the non-working case. I don't see anything in the software that might cause this issue. The MMC driver is pretty much stable in the latest releases assuming you are using the latest release only.
On that note, could you please confirm the exact SDK version you are using?
The logs show the U-Boot version as
U-Boot SPL 2025.01-00603-g674977ce0b8d-dirty (Jan 12 2026 - 15:26:03 +0530)
The commit "674977ce0b8d" is not present in the `ti-u-boot` repository and it must be coming from your changes made in the source code. From what I can tell, your U-Boot version is based on the U-Boot version (tag: 11.01.16) from the SDK v11.1.
If this is indeed the case, could you please confirm if you have made any changes in the MMC driver? Also, have you tested with the latest SDK as well?
Unless you have some custom changes in the MMC driver,
The issue should mostly be originating from the hardware. Please review the suggested schematics changes and see if that resolves the issue.
Hi Ninad,
Hello ,if there is issue in schematics How it is working properly in Kernel in 200MHz?
We dint faced any problems with uboot in 52Mhz and Kernel in 200 Mhz until now
A1. Unfortunately, an eMMC clock signal integrity issue has a potential to compromise booting and read/written data. How - some spurious clock transitions seen by the eMMC memory. To evaluate such "potential" I need to have the 52 MHz clock oscillogram with an improved measurement equipment (if possible - use at least a 200 MHz 2GSa/s oscilloscope) and the right setup - a probe with a ground spring and 200 MHz BW. If you do NOT have a better oscilloscope please provide a second oscillogram measuring output of a 10 or 50 MHz reference oscillator. In the 25 MHz oscillogram I see overshoots / undershoots which might still not cross Vih_min and Vil_max thresholds and does not cause spurious eMMC memory clock transitions but at 52 MHz and higher frequency this could change. Another consequence of undesired reflections (overshoot and undershoot) is that absolute maximal ratings for AM62L eMMC CLK output voltage are exceeded.
A2. The lack of a 0R series termination resistor placeholder alongside the eMMC_CLK signal trace contradicts with what TI Schematic Review checklist and Custom Board Hardware Design Guidance recommends for AM62L eMMC interface. I will internally discuss with our signal integrity expert.
On what basis these values are decided ? what are the other possible values which we can test ? why <0x6> in default
As Prashant already mentioned, access operations in eMMC HS200 mode demand precise timings. For this high speed mode an automatic tuning is performed in software, to find the optimal Rx (input) clock tap delay value. For selected HS200 mode, it is necessary to manually set a fixed Tx (output) clock tap delay value = 0x6 in bitfield MMCSD0: MMC_SSCFG_PHY_CTRL_4_REG [16:12]OTAPDLYSEL, which seems to be a consequence from the above Linux dts row.
Please versus the Section, MMCSD / MMC0 - eMMC/SD/SDIO Interface of the AM62L DS
Thanks
Best Regards
Anastas Yordanov
Hello Prashant Shivhare
To clarify our kernel works in 200Mhz itself 
also we had kept for eMMC stress test for long run we dint faced any issue .
But if the eMMC is in HS200 mode, we are facing issue in the U boot itself board fails to boot , as we previously discussed.
Note -"ti,otap-del-sel-hs200" if this is removed Uboot works in 200MHz and board boots but saw some failed condition in the kernel
[ 4.261834]
[ 4.268345] mmc0: Failed to initialize a non-removable card
[ 5.200499] sdhci-am654 fa00000.mmc: Power on failed
[ 5.241633] mmc1: SDHCI controller on fa00000.mmc [fa00000.mmc] using ADMA 64-bit
[ 5.249430] Waiting for root device /dev/mmcblk0p2...
in the long run
So we removed "mmc-hs200-1_8v" property in the uboot , Now as before uboot is in 52MHz and kernel is in 200Mhz but never saw the issue in kernel as well as uboot .
Our Concluded observations -
| Case | ti,otap-del-sel-hs200 |
mmc-hs200-1_8v |
U-Boot MMC Speed | Kernel MMC Speed | Observed Result |
|---|---|---|---|---|---|
| 1 | Present | Present | 200 MHz | 200 MHz | Board fails to boot with reset error or OSPI image load error |
| 2 | Removed | Present | 52 MHz | 200 MHz | Board boots, but sometimes fails with mmc0: error -1 during MMC initialization in kernel |
| 3 | Removed | Removed | 52 MHz | 52 MHz | No issues observed so far during testing |
Note- We had added thin insulated copper wire to probe at "eMMC CLK 10K Pull down resistor" this point And with 200MHz in U boot and 200MHz in kernel we dint faced the error In the same issue board
Thank you,
Waiting for your opinion on this
Regards,
Ninad
