Hello,
I have a few questions about the TLK10002. I plan to use the device to test a series of high speed signals. Here's my setup:
Scenario Overview
- I plan to use the low speed side of the TLK10002 (INA0, INA1, INB0 and INB1) for 4 channel parallel Error Detection
- I plan to use 4 channel data rates--synchronous from .5Gbps to 4.5Gbps on all 4 channels
- I plans to generate PRBS pattern: 2^7, 2^23, 2^31
- I plan to create a synchronous REFCLK=.5-4.5GHz/1/2/4/8/10/16/20/N for the TLK10002 at the above data rates
- I will use a HS PRBS verifier with the same matching PRBS pattern to verify that the bit stream is error free
Factory Request
- I want ta TI application group that has used the TLK10002 to confirm that the proposed test sequence will work
- I would appreciate any application notes related to BER calculation
- I would like all the schematics for the TLK10002 evaluation board
- TLK10002EVM
- Regarding the low speed side PRBS ED, the part has 4 low speed inputs in A and B portion of the IC
- The part can use all four inputs up to 2.5Gbps for regular operation and ED function
- Can I use all 4 inputs up to 4.5Gbps for PRBS ED function only?
-David