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DS80PCI800 Based PCI-E Edge-to-cable Card

jack dawson
Prodigy 70 points
Other Parts Discussed in Thread: DS80PCI800, SN65LVCP114, SN65LVCP1412, SN65LVCP1414

Hello,

     I have been tasked to build an active PCI-E Edge-to-cable solution based on FCI's Mini-SAS HD line of external cables. The plan would be to use the EEPROM's embedded on each end of the cable (or possibly a secondary EEPROM on the board) to store the configuration information and run the device as a SMBUS master on start up. From what I have read so far the DS80PCI800 looks like a relatively straightforward device to work with but I have a few questions: 

1)  Why should we go with a re-driver versus a re-timer or a switch in this application? What are the benefits of TI's re-driver solution over these other options?

2) I read on a previous comment that it is harder to get a link up and running with two re-drivers versus 1. How would you suggest setting up a link with two re-drivers?

3)  From my understanding of the PCI-E gen 3 protocol, on start up each link performs a training sequence to establish the optimal transceiver settings for the particular link. Does having two re-drivers in the link hinder this training sequence? I would assume the re-driven section of the link would appear completely transparent but I need to confirm this.

The attached picture shows a rough outline of our proposed link.

Thanks,

Jack Dawson  

  • 0
    TI__Mastermind 20820 points

    Hi Jack,


    1. If the loss in your link is a manageable amount a redriver is a much better solution than a retimer. A retimer is more expensive and requires additional external components for operation where as a redriver comes in a small package and in most cases will give the link the extra margin that is required for an error free link. Retimers do have a time and a place though but it is always good to explore several options when designing a cost effective error free link.

    2. Having two redrivers in a link can be challenging at times because the optimization of the link can be difficult. Redrivers are meant to provide a flat frequency response across your nyquist frequency so that your link appears loss less. Well when you cascade redrivers back to back it can become difficult to manage the amount of gain in the link and people who do not have the right equipment to examine their link end up over equalizing their signal any having a ton of trouble debugging their system. Understanding your systems topology is critical when cascading redrivers.

    3. Yes PCI-E Gen 3 does have a training protocol at start up and having two redrivers in your link can hinder this process because your training sequence can be corrupted. The PCI-E Gen 3 Tx and Rx PHYs try to equalize out the channel that is front of them. If the loss of the channel is greater than what the PHYs can handle (~25dB for PCI-3) it is common practice to place an equalizer in the link to aid the PHYs in the process. You have to be careful though because the PHYs try to pass a training signal back and forth that has some transmit equalization on it and if your equalizer is limiting the pre-emphasis will not make it through the equalizer uncorrupted. A limiting equalizer will actually clip the signal at its output either hi or low depending on how it interprets the incoming data. This is no good for an application like PCI-E 3. What you are looking for in this instance is a Linear Equalizer. A linear equalizer is a device that has an over all transfer function that can be adjusted by several knobs on the input and output of the device. It will pass training sequences distortion free and simply gain them up so that your PHYs can actually achieve a longer link than usual. With all that being said I think you should look into the SN65LVCP1414, SN65LVCP1412, and the SN65LVCP114 (10G Mux). I have several customers already using these devices in systems that incorporate SAS, KR, and PCI. The SN65LVCP1xxx is a linear equalizer with 14.2G of bandwidth and 17dB of gain at 7.1GHz. I have seen these devices extend a SAS3 link out to ~36dB of loss and achieve a 10^-12 BER without a problem. Please let me know if you have any more questions as I am glad to help.

    Regards,

    Michael Peffers

    Analog Applications Engineer