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Layout design for MDI Trace impedance control

Hak-Jin Jeong
Intellectual 350 points
Other Parts Discussed in Thread: DP83865

I posted  this question into industrial interface forum,

and later, I found Ethernet forum. so, I posted it again.

===================================================================================

I have one question about dp83849I. (Actually it may be general questions about MDI trace routing.)

 

According to design and layout guidelines, MDI signal traces should have 50 ohm to ground or 100 ohm differenctial impedance.

 

If I use 4 layer, 2T, 1oz PCB, in case of microstrip, the trace width should be more than 0.6mm to meet 50/100 ohm impedance. but your pin width is just max 0.27. How can I meet the impedance requirement?

Even in your DEMO board reference design (snlc021), your MDI trace( on the top layer ) width seems to be just less than 0.27.

If I used stripped line scheme, I should make some vias, but also, your design guideline recommend not to use via.

 

I am a little bit confused. I am very novice for ethernet.

please let me get more insights on this subject.

 

Thank you for your advice in advance.

Best Regards

Hak-Jin Jeong

  • 0
    TI__Mastermind 31600 points

    Hak-Jin,

    For the DP83849 EVM, the MDI traces at the pins are 10mil traces with a 10mil separation.  The top and bottom etch are 1.5oz finished copper.  The stack up is a 4 layer board with 6mils between layers 1 and 2 and 6 mils between layers 3 and 4.  For the MDI traces at the pins, these dimensions should result in 100 Ohm differential impedance. 

    We have a design and layout guide that includes some general guidance and some sample calculations of trace impedance for stripline and for microstrip.  It is available at:

    http://www.ti.com/lit/pdf/snla079

    In terms of signal integrity, an optimal layout for the MDI traces would be on a single layer and would have no vias.  However, this is not possible or practical in all implementations.  Stripline can be used for the MDI traces and vias would therefore be a necessary component of the construction.

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 350 points

    Thank you for your advice.

     

    Based on your trace/stack up dimension information, I found the cause.

    My PCB was 2.0t, so the stack up height was 12mils, that's why my calculated width was more than 0.6mm.

     

  • 0 in reply to Patrick OFarrell
    Prodigy 10 points
    I have a question regarding the same topic on the DP83865 PHY.

    Figure 18 of the DP83865's datasheet points that 50-ohm controlled impedance with respect to VDD or GND must be used. But on the AN-1263 which is the design guide application note, figure 8, it says that one should look for 50-ohm controlled impedance with respect to VDDA (2.5V). So which option is the correct?

    Alfredo