TLK10232_Packet_Loss

user4366098

Other Parts Discussed in Thread: TLK10232, TLK10232EVM

Hi!
I have a board ,there is a fpga and tlk10232 chip ,fpga sends test data to tlk10232 ,then tlk10232 sends data to fiber ,fiber loops data back to tlk10232 , tlk10232 sends the data back to fpga , fpga detects whether data is equal to the data it sends .
(FPGA<generate test data> --> TLK10232 --> Fiber<Loop back> --> TLK10232 --> FPGA < check the data > );
1.when fpga sends the same packet( the same length and data ),and the gap between packet is 16 bytes (about 2 data time ) ,there is no data error .
2.when fpga sends different packet ,the packet length is increasing from 100 to 1800 (each cycle begins:the first packet length is 100, the second packet length is 200 , the third packet length is 300,---,the last packet length is 1800, and then the next cycle ),every packet data begins from 64'h0102030405060708 , then 64'h0203040506070809, then 64'h030405060708090A,and so on until the end of the frame .and the gap between packet is 16 bytes (about 2 data time).Now ,sometimes ,fpga checks the loopback data , finds some packets have been lost ;because,one packet after another , packet length is cycle ,but its received packet length sometime is jump .

Who has some suggestions ? Thanks !!!
Best Regards!

over 9 years ago

0 Luis Omar Moran over 9 years ago

TI__Genius 16150 points

Hi,

1. How are you setting the device?

2. Have you performed a tuning of the device? Every system is different, so, user needs to adjust some parameters for the correct behavior of the device.

Regards!
Luis

0 user4366098 over 9 years ago in reply to Luis Omar Moran

Prodigy 100 points

Hi!

First ,thanks for your answer !

The Tlk10232 works at 10G-KR mode , before it works , configure the following register:

1.Device_addr(5'h07),register_addr(16'h0000),write_data(16'h2000);(Disable Auto Negotiation)

2.Device_addr(5'h01),register_addr(16'h0096),write_data(16'h0000);(Disable link training)

3.Device_addr(5'h01),register_addr(16'h00AB),write_data(16'h0003);(Enable 10GBASE-R FEC function )

4.Device_addr(5'h1E),register_addr(16'h8020),write_data(16'h03FF);(KR training to be configured manually instead)

5.Device_addr(5'h1E),register_addr(16'h0004),write_data(16'hD500);(High_Speed_ENTRACK+ EQPRE)

4.Device_addr(5'h1E),register_addr(16'h000E),write_data(16'h0008);(Channel datapath reset control);

then after about 2 seconds , fpga starts sending test packets , and through the tlk10232 , then the fiber loopback , then tlk10232 to fpga , fpga checks the received data , and sometimes , some packets are lost , not packet data error .

Another question , do pins "AMUXA" and "AMUXB" must be left unconnected ?Both of them are "Analog I/O","SERDES Channel A/B Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application." If both of them connected to GND , will affect the chip work ?

the board's power, clock ,have not find any problem .

Thanks !!!

Regards!

0 Luis Omar Moran over 9 years ago in reply to user4366098

TI__Genius 16150 points

Hi,

For SFI/XFI operation, please follow this procedure:

1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

4. Disable link training by writing 16’h0000 to 0x01.0096

5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.

6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.

7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

At this point the device should be properly configured.

Attached you will find a guideline to configure the device in several modes.

Regarding to AMUXA & AMUXB, if both are connected to GND, the chip would work ok, although the recommendation is left them floating. Even in the TLK10232EVM both have a jumper: Floating/GND.

I hope this helps.

Best Regards!

Luis Omar Morán Serna

High Speed Interface

SWAT Team

0 user4366098 over 9 years ago in reply to Luis Omar Moran

Prodigy 100 points

Hi,
thank you , it works .
I find the cause of the problem , when a packet after another packet ,and the gap between two packet is 16 bytes ( 2 64bit data time, about 12.8ns , the reference clock selection is 156.25 MHz ),then when fpga receives the packet loopback,the gap sometime is changed to zero . Is this normal ?
I suspect that the reason is the frequency difference between the TLK's reference clock(156.25MHz) and the FPGA's reference clock(156.25MHz) too much .
Although the tlk10232 has CTC(CLOCK TOLERANCE COMPENSATION) Fifo , the TX/RX_FIFO_DEPTH and TX/RX_CTC_WMK_SEL can be configured (Dev_addr=5'h01,Reg_addr=16'h8001,KR_VS_FIFO_CONTROL_1), but the gap between two packet sometimes is changed to zero , fpga sends the gap between two packet is two . Is this normal ?
Thanks !!!
Best Regards!

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TLK10232_Packet_Loss