SN65LVPE501 eye diagram fail for SIT g2 testing

Peter Tseng

Genius 5770 points

Other Parts Discussed in Thread: SN65LVPE501

Dear Sirs,

Is there any advise for customer issue for g2 testing fail on SN65LVPE501?

Customer had tried to change the DEx, OSx, and EQx setting but not work.

The SN65LVPE501 was designed on mini PCIe card and connect with system via PCie slot.

They also have another project design with SN65LVPE501 by different RD and its on system directly, not on card. In that project, the g2 testing is OK.

Below are the eye diagram snap.

Please help to give me some suggestion where I need to pay attention about customer design.

Thanks.

over 7 years ago

0 Moises Garcia over 7 years ago

TI__Mastermind 23815 points

Hi Peter,

Could customer share the eye diagram of CP1?

Could they share their layout for review?

Regards

0 Peter Tseng over 7 years ago in reply to Moises Garcia

Genius 5770 points

Hi Sir,

Thanks for your reply!

May I know what is the CP1 signal?

Below is what I found about CP1. Is that what you mean?

From the data, it seems for USB3 testing! Is it also compatible for PCIe signal testing?

Thanks.

0 Moises Garcia over 7 years ago in reply to Peter Tseng

TI__Mastermind 23815 points

Hi Peter,

Yes I'm sorry I was reviewing USB eye diagrams as reference.

What I would like to see is the eye diagram for repeating 1010

Could you share layout too?

Regards

0 Peter Tseng over 7 years ago in reply to Moises Garcia

Genius 5770 points

Dear sir,

I has sent the file to you via private message.

Thanks.

0 Moises Garcia over 7 years ago in reply to Peter Tseng

TI__Mastermind 23815 points

Hi Peter,

Thanks for sending the files, I was unable to open it because they are gerber files, do you have Altium, pads, expedition, or allegro file?
Could you get the eye diagram for 01010101... sequence?

Regards

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SN65LVPE501 eye diagram fail for SIT g2 testing