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DP83822I: DP83822I RMII Slave mode 50Mhz radiated emission issue

RongFeng Yan
Prodigy 70 points
Part Number: DP83822I

Hi Sir,

In DP83822I RMII Slave mode, which RMII signals are 50Mhz?

Are they: RX_D0,RX_D1,RX_D3,TX_D0,TX_D1?

If the 50Mhz radiated emission is higher, what is the solution? Add 33ohm series resistor at each 50Mhz RMII signals between PHY and MAC(in MCU)?

Following is part of schematics around DP83822I. Just for the reference.

Thank you.

Regards

Rongfeng

 

  • 0
    TI__Mastermind 19780 points
    Hi RongFeng,

    Yes, the signals you pointed out are all 50MHz maximum. RX_D0, RX_D1, RX_D3 (50 MHz output clock), TX_D0, TX_D1

    A series limiting resistor is helpful, as well as following all layout best practices for high speed interfaces.

    www.ti.com/.../spraar7g.pdf

    www.ti.com/.../scaa082a.pdf

    The above 2 app notes describes the best practices for routing your 50 MHz signals.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 70 points

    Hi,

    Is there any way to change internal register settings for controlled slew rate on those 50Mhz signals?

    If yes, which are the registers?

    Regards

    Rongfeng

  • 0 in reply to RongFeng Yan
    TI__Mastermind 23675 points
    Hi Rongfeng,

    There is no slew rate control for those pins.
  • 0 in reply to Ross Pimentel
    Prodigy 70 points

    Hi,

    Besides series resistor at 50MHz signal, and pay attention the layout routing, is there any other way to reduce the 50MHz harmonics emission?

    We will analyze and try the different ways.

    Thank you.

  • 0 in reply to RongFeng Yan
    Prodigy 70 points

    Do you think using series ferrite bead (Z<50ohm at 50MHz, and >100ohm at higher frequency like 200MHZ, 300MHZ) at 50M clock line, is able to reduce the 50M harmonics emission?

    Without affecting the clock waveform quality.

  • 0 in reply to RongFeng Yan
    TI__Mastermind 23675 points
    Hi RongFeng,

    I have not tried that approach before. It does sound like an interesting way to reduce this emissions. However, I am hesitant to recommend this because you do not want to completely filter out the higher frequencies because that will start affecting your rise/fall times.
    The 33 ohm series resistors did not improve emissions?
  • 0 in reply to Ross Pimentel
    Prodigy 70 points

    Hi, 

    I just want to know more solutions in case series 33R is not enough.

    Due to space limitation, we can not put 33R very near PHY, but a little bit far away, so this may reduce the effect of improvement.

    Another point, do you think the VDDIO current path is important on the emission? 

    We find that the GND via is not close to the VDDIO decoupling capacitor, this may cause large GND loop, is it correct?

  • 0 in reply to RongFeng Yan
    TI__Mastermind 23675 points
    Hi FongFeng,

    That could be another issue. You want to minimize the ground loops.
    Do you also have solid return paths under all traces? No ground breaks that signal traverse, correct?

    Do you have any signals that are going from one layer to another? Have you also tried adding a ground via stitch next to those signal vias to reduce the ground loop?

    On the MDI (cable interface side) have you tried adding some line capacitance to slow the edge rates down? You can try adding up to 10pF to TD+/- and RD+/- pins.
  • 0 in reply to Ross Pimentel
    Prodigy 70 points

    Hi,

    Thanks for your suggestion.

    We will analyze and try to improve the GND and via location to minimize ground loop.