DS280DF810: PRBS operation

Hi Curtis,

We have a couple of FAQs discussing this topic - using integer multiple clock to generate PRBS. Please note links below:

Register settings for prbs generation:
e2e.ti.com/.../701766

Using GUI to generate PRBS pattern:
e2e.ti.com/.../701759

Regards,,nasser

Thank you for pointing to these FAQs. To answer your question, the setup described (using an external input at the RX input) does not resolve my issue. Please refer to the specific wording of my question and further details to explain my setup and intent:

I have a QSFP28 test card design (intended to test 10 Gbps or 25 Gbps QSFP28 devices) that consists of a QSFP28 card cage and a DS280DF810 device. The odd-numbered DS280DF810 RX inputs are driven from the QSFP28 connector outputs, and the even-numbered DS280DF810 TX outputs are driven to QSFP28 connector inputs. The only other pins connected to test card circuitry are the DS280DF810 twenty-five MHz clk input, the SMBus pins, and general I/O pins (reset, address, etc.). The DS280DF810 test pins have pulldown resistors on them.

The design works great for flow-through testing of the QSFP28 at 10 and 25 Gbps (x4) when I set up the crosspoint switch to fanout the odd-numbered RX input to both the even and odd-numbered channel of each pair, and connect the DUT QSFP28 module optical I/O connectors to a 40Gbps / 100Gbps BERT tester. Thus, I understand that the CDR will lock when the RX input is driven with an appropriate data stream (or clock, as described in the threads you mentioned).

However, I would like to make use of the internal PRBS generator of one QSFP28 test card to drive the PRBS checker of the next downstream identical QSFP28 test card - or, in a simpler test setup, loop a single test card's QSFP28 optical IO to itself. In the latter case, there is no available external data stream to create CDR lock on the PRBS generator channel signal path.

So, my question may have to be answered by the IC design team or by the IC test team - I want to know if there is a "test" mode or register settings / sequence available (perhaps through reserved registers) to get the PRBS generator to free-run without an initial "seed" RX input to create CDR lock. I realize that the CDR has to lock to some reference to keep the loop stable. I'm thinking that the designers, in conjunction with the IC test engineers, might have implemented an IC-test-only method of achieving CDR lock to test the PRBS generator output: perhaps by forcing a test sequence that enables PRBS operation at the free-running VCO frequency (unlikely to be stable), or, by forcing the CDR to lock (at a specific output frequency such as 10 or 25 Gbps) to an internally generated multiple of the 25 MHz oscillator input or the internally derived 10 MHz domain clock.

I understand that this is a special request, and it is perfectly acceptable to remove this post and respond privately with register setup code (such as in the register setting thread) or GUI register settings. Please forward my request to the appropriate person if necessary. I will not have access to my test setup until 7/17/18 as I am away from the office. Thank you very much in advance!

Hi Curtis,

I understand you want to use 25MHz clock to generate PRBS pattern. I have to check on this and will let you know. Meanwhile here is my email address: Nasser.mohammadi@ti.com.

Regards,,nasser

Please see e-mail to Nasser.mohammadi@ti.com

Hi Nasser,

Thanks for the information. Based on the wording of your answer, it seems that it might be possible to sync all eight CDRs from one input. It would be very useful for me to know how I can configure the DS280DF810 to accept one high-speed clock to sync multiple or all eight CDRs. Can you please inquire on which input(s) could be thus used, and what register settings are required to sync all eight CDRs from one input?

Thanks in advance, Curtis