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DS90UB954-Q1: Pattern Generator Excel Calculation Sheet

Ting Ye
Genius 11800 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: ALP,

Hello Team,

Thank you for adding FPD-LINK script in ALP (Analog LaunchPAD v1.57.0010) PreDefScripts folder to help us generate correct pattern.

Below is DS90UB954-Q1 Pattern Genenator excel calculation for RGB888 1280x720p 30fps.

Could you help me double check if the calculation is correct?

Pattern Gen 954_V3.xlsx

Thanks!

Regards,

Ting

  • 0
    TI__Mastermind 30515 points
    Ting,
    the PCLK is based on internal oscillator if internal clock is selected.
    for this case, you should use 100MHz as "PCLK" which is use inside UB954 to calculation the timing (line_pd). This "PCLK" is NOT display panel video's PCLK.

    you can refer to d/s on pattern gen. for details.


    regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    TI__Genius 11800 points

    Hello Steven,

    Thank you for the prompt supports!

    I change the PCLK to 100MHz and update it to below file. 

    Pattern Gen 954_V4.xlsx

    Thank you!

    Regards,

    Ting

  • 0 in reply to Ting Ye
    TI__Mastermind 30515 points
    most are correct. but the Line_pd is incorrect.
    please see d/s on line_pd (0X0C/0X0D) description, it is calculated by: 1000000000(ns)/30(fps)/750 (lines/frame) x10 (ns/bit)= ~4444.


    best regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    TI__Genius 11800 points

    Hello Steven,

    Thank you for the prompt supports!

    I updated the line period to below V5 file.Pattern Gen 954_V5.xlsx

    Thank you!

    Regards,

    Ting

  • 0 in reply to Steven(Shenzhen) Shi
    TI__Intellectual 2100 points

    Hi Steven,

    In the previous post you mention that the PGEN_LINE_PD calculation is based on the PCLK rate. However in your calculation above, and the datasheet, we just state that the line period is in 10-ns units, and don't reference the PCLK at all.

    Does this description just assume that the internal oscillator is being used, and therefore PCLK = 100 MHz (which would give us a 10-ns time base). If an external oscillator is being used, wouldn't the equation change to the following:

    IF this is the case, this description should be updated to reflect the fact that the line period is based on the PCLK, rather than assuming 10-ns.

    Thanks for the support as always!

    Regards,

    Andy

  • 0 in reply to Andy Snawerdt
    TI__Mastermind 30515 points
    Andy,
    :( I understand your confusion.
    For UB954, the FPD-Link is fixed at ~4Gbps based on external ref. clock. So its "PCLK" is referred as 100MHz (4Gbps/40) which is used for Pattern timing calculation. In other words, this is the "10ns". BUT this "PCLK" is different from the sensor video output's PCLK.

    regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    TI__Intellectual 2100 points

    Hi Steven,

    Thanks for the quick response.

    Is this only true for the synchronous clocking mode? See below for a snippet from the UB954 datasheet.

    In my use case, I am doing exactly as is highlighted. The UB953 utilizes an external reference clock (CLK_IN = 42 MHz), which in turn means the line rate = 42 MHz * 80 = 3.36 Gbps.

    Would this make the pattern timing calculation utilize 84 MHz (3.36Gbps/40) instead?

    Thanks for the help!

    Regards,

    Andy

  • 0 in reply to Andy Snawerdt
    TI__Mastermind 30515 points
    Yes, for UB953, it uses the 84MHz clock as PCLK freq. as UB953's operation freq. is based on this. so the pattern gen. timing also is dependent on this base clock.

    regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    TI__Intellectual 2100 points

    Perfect! Thanks for all the help Steven!

    Regards,

    Andy