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This device works differently than most buffers. It provides its own current source on the A side of the device so it does not use a pull up resistor on that side. In order for this device to see a low, the master/slave must sink all of our device’s current (1mA).
Any master or slave connected to this device basically needs to have an Rds(on) of ViLc/1mA or 0.150V/1mA. This means the master or slave must have an Rdson(max) <= 150 ohms. This is fairly large for an I2C pull down FET.
Therefore the customer should not be concerned with the VoL of their master/slave but instead be looking at Rds(on).
"May I know if the ViL for SDAA/SCLA should be aligned with VILC for I2C communication to operate correctly?" SCLA does not because it is unidirectional in most cases (in I2C it is). It only needs to meet ViLC if you expect the slave to perform clock stretching.
From my earlier explanation, the customer should find what their Rdson of their master/slave is to see if it is compatible with our device. They should not be looking at VoL of their master/slave.
