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DS90UB914Q-Q1: DS90UB914Q-Q1

jakir hussain
Prodigy 30 points
Part Number: DS90UB914Q-Q1

HI ,

I am using DS90UB914 de-serailizer to interface digital camera which having ds90ub913 in it .

my camera is YUB422 8 bit.but i am using de-serailizer in 10 bit mode .i am getting output from de-serializer but also getting parity error in parity error resister .one more thing in status resister of ds90ub914  lock bit is continue keeps toggling .

any one tell me is this due camera is 8 bit and de-serializer is 10 bit ????  

  • 0
    TI__Expert 7935 points
    Hello-

    Improper configuration of the video format in the deserializer would affect what the deserializer output.

    The parity errors and toggling of the lock bit indicate issues with the FPD-Link III transmission (communication between serializer and deserialzier).

    Is the PCLK provided to the DS90UB913 meeting the requirements given in the datasheet (frequency, jitter, duty cycle, etc.)?

    Is the transmission channel (PCB, cables, connectors) designed to handle high-speed FPD-Link III signals?

    Regards,
    Davor
  • 0 in reply to Davor Glisic
    Prodigy 30 points

    Hi Davor

    Is the PCLK provided to the DS90UB913 meeting the requirements given in the datasheet (frequency, jitter, duty cycle, etc.)-yes it about 61 Mhz from camera .

    Is the transmission channel (PCB, cables, connectors) designed to handle high-speed FPD-Link III signals- yes all design for high speed link as given in datasheet.

    but i have concern with video format camera giving 8bit YUV format but de-serailizer have option only for 10 bit and 12 bit only .Is camera should be 10 bit or it will work with 8 bit as well??

    regards

    Jakir Hussain

  • 0 in reply to Davor Glisic
    Prodigy 30 points

    Hi Davor,

    i have tryed a lot to debug the issue but unable to find .i have tested by clock it seems fine having no jitter .
    when i disable the crc & parity check in de-serializer then in this case i am getting continue PCLK and LOCK pin continues high but in this case i am not getting any data output .is there is any other configuration by which i could bypass parity and crc checking to get the valid output ??

    is there any other debug method to find the issue?

    below you can find clock and signal output.

    Jakir hussain

  • 0 in reply to jakir hussain
    TI__Expert 7935 points
    Hello-

    Are you sending power over coax from the 914 to 913 side? If so, can you disable that and power each device separately?

    Do you have a good controlled impedance on the FPD-Link III interconnect (PCB, connectors, cable)?

    Can you try different cable lengths and see if it affects the performance?

    Can you try lowering the PCLK and see if it affects the performance?

    Regards,
    Davor