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DS42MB100: PCIe Gen1 link training with DS42MB100

Jijesh Janardhanan
Prodigy 120 points
Part Number: DS42MB100
Other Parts Discussed in Thread: HD3SS3415, DS125MB203, HD3SS3412

Hi,


We have used DS42MB100 as a 2:1/1:2 Mux/buffer in PCIe Gen1 interface. I am raising this question since this device is not explicitly targeted for PCIe designs. Please let me know if you see any issues here. PCIe interface of both host and end point are CML type. PCIe link training is not happening when the signalling is through DS42MB100. We have tried disabling EQS, EQL and DEL & DES set to 0 dB. Still link training failed.

When we bypassed DS42MB100, PCIe link training is passing successfully.
Is it possible to completely disable buffering action and use the device in just 2:1/1:2 mux? Let us know possible solution

Thanks,
Jijesh

  • 0
    TI__Mastermind 43795 points

    Hi Jijesh,

    The DS42MB100 is not optimized for PCIe applications.  The major issue will be for PCIe to detect the DS42MB100 input termination.  If you add an external termination on each high speed signal to VDD it may overcome the link initialization problem.

    Another option would be to use an active DS125MB203 or passive mux HD3SS3412 / HD3SS3415.

    Regards,

    Lee