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DP83630-EVK: CLK_1588(SMA)/CLK_OUT(Pin 24 of DP83640) output stuck at GND (has no output)

Part Number: DP83630-EVK
Other Parts Discussed in Thread: ALP, DP83640T-EVK, DP83640

I have two DP83630-EVK(s), connect them with CAT5 cable (1meter long).

Then LED SPEED and LINK lights up, it seems like them connect successful.

I use a PC with Windows XP , then installed drivers and ALP software.

By using ALP write reg 0x14 as 0x0004, CLK_1588/CLK_OUT still stuck at GND.

Connect Pic: 

ALP settings :

Write Reg 0x14 as 0x0004


  • Hi,

    Can you try reading basic register 0x0000 and 0x0001 ? It will confirm whether your access to MDIO/MDC is working or not.

    We use USB-MDIO software and MSP430LP for MDIO/MDC access.

  • Yes, I can read reg 0x00 and 0x01.

    In one DP83640T-EVK whose Physical Address is 0,its reg 0x00 is 0x3100. And another one reg 0x00 is 0x3100.

    And their reg 0x01 are 0x78ED.

    Reg 0x00 = 0x3500 shows us Bit 10 : Isolate is 0x1.

    Should I write Reg 0x00 as 0x3100, and then write 0x14 as 0x0004?  (Is it right?)

  • Hi,

    Good to know your MDIO/MDC is good.

    For CLK_OUT as per datasheet, you shall configure register 0x001C. How did you came to know that you to configure 0x0014 ?

  • I can enable CLK_OUT after I Set 0x001C as 0x0004.

    After I write regs as AN-1729, 3.2 Phase Alignment

    It shows me ,

    Example: Phase alignment of a 10 MHz clock output:

    Enable the Event monitor and get the event timestamp: – Write 0x1C0F to the PTP_EVNT register.

    – Write 0x5C0F to the PTP_EVNT register.

    The first write sets up a single event capture for CLK_OUT/GPIO12 with Event 7 (though any event may be used).

    The second write does the same plus it enables the capture.

    – Read the PTP_ESTS register for bit 0 set. If not, wait and repeat this step.

    – Once bit 0 of PTP_ESTS has been set, determine the event timestamp length (1-4 16-bit words) by adding 1 to bits 7:6 of the PTP_ESTS value.

    – Ensure the Event number is 7, (the PTP_ESTS value bits 4:2 equal 7).

    – Ensure the event was a rising edge. This is indicated by the value of PTP_ESTS bit 5 equaling 1.

    – Read the PTP_EDATA register. The event timestamp is returned as follows: • Event nanoseconds bits 15:0 • Event nanoseconds bits 29:16 • Event seconds bits 15:0 • Event seconds bits 31:16

    But two DP83640T-EVK CLK_OUT can not be synchronous with another one. And PTP_ESTS is still 0.

    Is there any example of register map? I need two synchronous CLK_OUT output between DP83640T-EVK.

    Like AN-1730 Figure 3 DP83640 With Synchronous Ethernet Mode Enable in a Point to Point Network Topology

  • Unfortunately, I don't readily available example to share.

  • Hi,

    I am closing this thread. Incase you still have further questions, please open new thread and provide reference to this thread.