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TLK10031: Bring up procedures for 10GbE optical interface

Mohammad Abdelilah
Intellectual 290 points
Part Number: TLK10031
Other Parts Discussed in Thread: TLK10232

Our setup for the TLK10031 is:

- HS side: connected using SFP+ optical connector to the SFP+ of another PCI card connected to a PC at 10G rate.

- LS side: connected to 4 channels XAUI for TX and 4 channels for RX at rate of 3.125 Gbps implemented on a Zynq7000 FPGA. A 10GbE MAC IP is also implemented.

- MDIO signals: connected to the FPGA.

- Reference clock is connected to an 156.25 MHz oscillator.

- ST, Mode_SEL and PRBSEN are connected to pin headers and can be set as needed.

- TESTEN is pulled low.

What we were able to achieve:

1. Communicate with the PHY using MDIO to read registers and configure CLKOUT. We were able to receive CLKOUT successfully.

What we are trying to achieve:

1. Follow specific bring up procedures to get our test setup mentioned above to fully work. We found this 4048.tlk10232_BringupProcedures_v2.pdf document but we couldn't find the procedures suitable for our setup. Can you please point to which of the mentioned cases is suitable to us or guide us on how to get this setup to run successfully?

Your help is much appreciated.

Regards.

  • 0
    TI__Genius 10250 points
    Hello,

    We will look into this and get back to you as soon as we can. Due to the holidays in the US, it may take longer to respond.

    Regards,
    Yaser
  • 0 in reply to Yaser Ibrahim
    Intellectual 290 points

    Hello Yaser, merry christmas!

    Do you have any updates on this?

  • 0 in reply to Mohammad Abdelilah
    TI__Guru 64326 points

    Mohammad,

    See below for basic steps to achieving a successful bring up. Please let me know if you are having any issues with these steps.

    For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:

    1. Reset device (write a 1'b1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096

    5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.

    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.

    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3. (At this point the device should be properly configured).​

  • 0 in reply to Malik Barton57
    Intellectual 290 points
    Hi Malik, thanks for your reply.

    We tried the 7 mentioned steps and followed pages 10-13 in the bring up procedures document but couldn't get the loop back test to work as mentioned by my colleague in this topic: e2e.ti.com/.../760354

    I prefer if we can move all the discussion to the other topic for faster follow up by the team.
  • 0 in reply to Mohammad Abdelilah
    TI__Guru 64326 points
    Mohammad,

    I will switch over to the E2E post located here: e2e.ti.com/.../760354

    I will mark this thread as "TI thinks resolved" and continue responding on the thread linked above.