DS110DF410: A question about retimer DS110DF410 for clock recover

1. The Retimer chip has 25M refclk output. How is the clock generated inside the chip? Is it the recovered from CDR? Can it be used as the recover clock of syncE.
   • This output clock signal is simply a buffered version of the REF_CLK input signal.
   • The REF_CLK signal cannot be used as recovered clock for syncE. This clock signal does not feed into the high-speed data path. it merely serves as a reference for the retimer low speed digital logic
     
2. shown in the diagram below, the superior equipment sending signals to the Retimer, Retimer inside will have the CDR, and recover the clock, then then send it to the CPU, could you tell me the difference between the clock in position-1(before the retimer ) and the clock in position-2 (after the retimer). (Will the clock and PTP information be out of alignment with the upper level equipment with delay, frequency deviation, etc?). Is there anything wrong with syncE clock that CPU recovered from position 2? Is it necessary for the CPU to access the CDR in the retimer through I2C? CPU reads some adjustment parameters in the CDR to adjust the clock from the retimer to achieve the synchronization with the clock in position 1?

• The TI retimer does not output the recovered clock. it simply outputs a retimed version of the input data
• The output data will be exactly the same as input data, with some latency added in the order of ~200ps
• The retimer high-speed output will bear a strict clock-phase relationship with its input data, as the locked CDR has both phase and frequency lock with the input data
  

Regards,

Rodrigo Natal

HSSC Applications Engineer