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XIO2001: questions on XIO2001

Garrick Dai
Intellectual 1660 points
Part Number: XIO2001

HI Team,

My customer use XIO2001 and have below questions to check. Please help. Thanks.

1, If use external 25MHz crystal, does Pin F3(CLK) need to connect with Pin B11(CLKOUT6) ?

2, If use 25MHz crystal, can PCI bus clock operate in 66MHz or not?

B.R,

Garrick Dai

  • 0
    TI__Expert 8165 points

    Hello-

    Just to confirm, you're planning to provide an external 25 MHz clock source to pin F3 (CLK)?

    Regards,
    Davor

  • 0 in reply to Davor Glisic
    TI__Intellectual 1660 points

    Hi Davor,

    Customer use the device first time. They need to confirm below--

    1, if not use external crystal/clock, how to design? does Pin F3 need to connect CLKOUT6?

    2, if use external crystal of 25MHz, does Pin F3 need to connect CLKOUT6 or not?

    3, How to configure PCI bus clock to 66MHz if use external 25MHz crystal? 

    Thanks,

    Garrick Dai

  • 0 in reply to Garrick Dai
    TI__Expert 8165 points

    Hello Garrick,

    1.  If not using an external clock, the CLK pin needs to be connected to CLKOUT6 pin as detailed in Figure 3 of the XIO2001 Implementation Guide (scpa045d).  Note that the title of the Figure 3 is a bit deceiving.  "PCI Bus Clock Configuration with an External Clock Feedback" would be more accurate.

    2. If using an external clock, the CLK pin does not need to be connected to CLKOUT6 pin.  The trace length relationship between the synchronous bus signals and the external clock signals is still required to meet PCI bus setup and hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control register at offset D8h. Plus, the XIO2001 clock run feature must be disabled with external PCI bus clocks because there is no method of turning off external clocks. 

    3. The XIO2001 has options providing for four different PCI clock frequencies: 25 MHz, 33 MHz, 50 MHz,
    and 66MHz. The clock frequency provided is determined by the states of the M66EN and
    PCLK66_SEL terminals at the de-assertion of PERST .  For 66 MHz operation, both PCLK66_SEL and M66EN pins should be pulled high.  For more information, please review Section 4 of the XIO2001 Implementation Guide (scpa045d).

    Regards,

    Davor