I'm trying to figure out how to interface the low speed side of the TLK10xxx family (specifically the TLK10232) to normal FPGA IOs (specifically to a Xilinx Artix FPGA) for data rates up to 1.25Gb/s per lane on the low speed side.
I've searched the high speed interface forum as well as the TLK10xxx specific posts but there is no definitive answer it seems, even the TI technical support couldn't provide any conclusive input yet.
The TLK datasheet lists 100-800mV for the LS receiver and 250-2000mV for the reference clock inputs while the Artix datasheet says that at least 250mV can be expected on LVDS outputs. Both sides have internal termination and the data is 8b10b encoded so to me it looks like AC coupling via two capacitors (per lane) should be fine to drive those inputs.
On the TLK to FPGA side, the LS transmitter swing can be configured between roughly 200mV and 1V and uses 8b10b coding as well, again, internal termination is available so simple AC coupling should in my opinion be more than enough to get reliable data transfers.
Nevertheless, I would be very grateful to get a conclusive answer to the question:
"What are the minimal required parts to connect the low speed inputs and outputs of the TLK10xxx family to a typical Xilinx FPGAs (e.g. Artix) I/O ports (preferably configured as LVDS)"
Many thanks in advance,
Herbert
