SN65DSI83: SN65DSI83, Propiety initializaton, clock setting

Mateus Nil

Part Number: SN65DSI83

Hello,

I am testing SN65DSI83 as 4 lines MIPI bridge to 4 lines LVDS (WF101GTYAPLNG0#). LVDS pattern works fine, so I think that LVDS hardware is ok.

When I disable pattern (register 0x0C, bit 4 don't set high) and connect to MIPI source then my display is dark.

My display need 72Mhz LVDS clock so I use external source for it. Can I use source of MIPI signal with the same frequency as LVDS clock?
When I set burst MIPI In DSI tuner, then program show error about minimum frequency is more than 216Mhz, but when I set non-burst this error don't occure. Can you explain it ?

In attachment is my configuration IC. Can you check it ? Maybe it is easy mistake.

SN65DSI183.c

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#include "SN65DSI183.h"
I2C_HandleTypeDef hi2c1;
#define SN65_reg_SOFT_RESET                     0x09
#define SN65_reg_LVDS_CLK                   0x0A
#define SN65_reg_MIPI_CLK                   0x0B
#define SN65_reg_PLL_EN                     0x0D
#define SN65_reg_CHA_DSI_LANES                  0x10
#define SN65_reg_CHA_DSI_DATA_CLK               0x11
#define SN65_reg_CHA_DSI_CLK_RANGE              0x12
#define SN65_reg_LCD_SET                    0x18
#define SN65_reg_LVDS_VOCM_VOD                  0x19
#define SN_65_CHA_REVERSE_LVDS                  0x1A
#define SN_65_CHA_LVDS_CM_ADJUST                0x1B
#define SN_65_CHA_ACTIVE_LINE_LENGTH_LOW            0x20
#define SN_65_CHA_ACTIVE_LINE_LENGTH_HIGH           0x21
#define SN_65_CHA_VERTICAL_DISPLAY_SIZE_LOW         0x24
#define SN_65_CHA_VERTICAL_DISPLAY_SIZE_HIGH            0x25
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#include "SN65DSI183.h"

I2C_HandleTypeDef hi2c1;

#define SN65_reg_SOFT_RESET 					0x09
#define SN65_reg_LVDS_CLK 					0x0A
#define SN65_reg_MIPI_CLK 					0x0B
#define SN65_reg_PLL_EN 					0x0D
#define SN65_reg_CHA_DSI_LANES 					0x10
#define SN65_reg_CHA_DSI_DATA_CLK 				0x11
#define SN65_reg_CHA_DSI_CLK_RANGE 				0x12
#define SN65_reg_LCD_SET 					0x18
#define SN65_reg_LVDS_VOCM_VOD 					0x19
#define SN_65_CHA_REVERSE_LVDS					0x1A
#define SN_65_CHA_LVDS_CM_ADJUST				0x1B
#define SN_65_CHA_ACTIVE_LINE_LENGTH_LOW			0x20
#define SN_65_CHA_ACTIVE_LINE_LENGTH_HIGH			0x21
#define SN_65_CHA_VERTICAL_DISPLAY_SIZE_LOW			0x24
#define SN_65_CHA_VERTICAL_DISPLAY_SIZE_HIGH			0x25
#define SN_65_CHA_SYNC_DELAY_LOW 				0x28
#define SN_65_CHA_SYNC_DELAY_HIGH				0x29
#define SN_65_CHA_HSYNC_PULSE_WIDTH_LOW				0x2C
#define SN_65_CHA_HSYNC_PULSE_WIDTH_HIGH			0x2D
#define SN_65_DATA_TYPE						0x2E
#define SN_65_CHA_VSYNC_PULSE_WIDTH_LOW				0x30
#define SN_65_CHA_VSYNC_PULSE_WIDTH_HIGH			0x31
#define SN_65_CHA_HORIZONTAL_BACK_PORCH				0x34
#define SN_65_CHA_VERTICAL_BACK_PORCH				0x36
#define SN_65_CHA_HORIZONTAL_FRONT_PORCH			0x38
#define SN_65_CHA_VERTICAL_FRONT_PORCH				0x3A
#define SN_65_CHA_TEST_PATTERN					0x3C
#define SN_65_DSI_STRUCTURE_DATA_TYPE				0x3E

int sn65_init(void) {
	HAL_GPIO_WritePin(SN65_EN_PORT, SN65_EN_PIN, GPIO_PIN_RESET);
	HAL_Delay(10);
	HAL_GPIO_WritePin(SN65_EN_PORT, SN65_EN_PIN, GPIO_PIN_SET);
	HAL_Delay(10);

	/*SOFT_RESET*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_SOFT_RESET, 0x00);
	/*PLL_EN_STAT, LVDS_CLK_RANGE, HS_CLK_SRC*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_LVDS_CLK, 0x04);
	/*PLL_EN_STAT, LVDS_CLK_RANGE, HS_CLK_SRC*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_MIPI_CLK, 0x00);
	/*PLL_EN set LOW - disable*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_PLL_EN, 0x00);
	/*CHA_DSI_LANES - 4lines*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_CHA_DSI_LANES, 0x26);
	/*SN65_reg_CHA_DSI_DATA_CLK*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_CHA_DSI_DATA_CLK,
			0x00);
	/*SN65_reg_CHA_DSI_CLK_RANGE*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_CHA_DSI_CLK_RANGE,
			0x2B);
	/*SN65_reg_0x13, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x13, 0x00);
	/*SN65_reg_LCD_SET format, mode, polarity DE, HS, VS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_LCD_SET, 0x78);
	/*SN65_reg_LVDS_VOCM_VOD*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_LVDS_VOCM_VOD, 0x00);
	/*SN_65_CHA_REVERSE_LVDS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_REVERSE_LVDS, 0x01);
	/*SN_65_CHA_REVERSE_LVDS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_LVDS_CM_ADJUST,
			0x00);

	/*LVDS Pattern Generation*/
	/*SN_65_CHA_ACTIVE_LINE_LENGTH_LOW*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_ACTIVE_LINE_LENGTH_LOW, 0x00);
	/*SN_65_CHA_ACTIVE_LINE_LENGTH_HIGH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_ACTIVE_LINE_LENGTH_HIGH, 0x05);
	/*SN65_reg_0x22, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x22, 0x00);
	/*SN65_reg_0x23, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x23, 0x00);
	/*SN_65_CHA_VERTICAL_DISPLAY_SIZE_LOW*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_VERTICAL_DISPLAY_SIZE_LOW, 0x20);
	/*SN_65_CHA_VERTICAL_DISPLAY_SIZE_HIGH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_VERTICAL_DISPLAY_SIZE_HIGH, 0x03);
	/*SN65_reg_0x26, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x26, 0x00);
	/*SN65_reg_0x27, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x27, 0x00);
	/*SN_65_CHA_SYNC_DELAY_LOW*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_SYNC_DELAY_LOW,
			0x20);
	/*SN_65_CHA_SYNC_DELAY_HIGH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_SYNC_DELAY_HIGH,
			0x00);
	/*SN65_reg_0x2A, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x2A, 0x00);
	/*SN65_reg_0x2B, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x2B, 0x00);
	/*SN_65_CHA_HSYNC_PULSE_WIDTH_LOW*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_HSYNC_PULSE_WIDTH_LOW, 0xA0);
	/*SN_65_CHA_HSYNC_PULSE_WIDTH_HIGH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_HSYNC_PULSE_WIDTH_HIGH, 0x00);
	/*SN_65_DATA_TYPE*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_DATA_TYPE, 0x00);
	/*SN65_reg_0x2F, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x2F, 0x00);
	/*SN_65_CHA_VSYNC_PULSE_WIDTH_LOW*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_VSYNC_PULSE_WIDTH_LOW, 0x17);
	/*SN_65_CHA_VSYNC_PULSE_WIDTH_HIGH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_VSYNC_PULSE_WIDTH_HIGH, 0x00);
	/*SN65_reg_0x32, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x32, 0x00);
	/*SN65_reg_0x33, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x33, 0x00);
	/*SN_65_CHA_HORIZONTAL_BACK_PORCH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_HORIZONTAL_BACK_PORCH, 0x50);
	/*SN65_reg_0x35, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x35, 0x00);
	/*SN_65_CHA_VERTICAL_BACK_PORCH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_VERTICAL_BACK_PORCH,
			0x0a);
	/*SN65_reg_0x37, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x37, 0x00);
	/*SN_65_CHA_HORIZONTAL_FRONT_PORCH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE,
	SN_65_CHA_HORIZONTAL_FRONT_PORCH, 0x50);
	/*SN65_reg_0x39, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x39, 0x00);
	/*SN_65_CHA_VERTICAL_FRONT_PORCH*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_VERTICAL_FRONT_PORCH,
			0x0A);
	/*SN65_reg_0x3B, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x3B, 0x00);
//	/*SN_65_CHA_TEST_PATTERN*/
//	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_CHA_TEST_PATTERN, 0x11);
	/*SN65_reg_0x3D, without description in DS*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, 0x3D, 0x00);
	/*SN_65_DSI_STRUCTURE_DATA_TYPE*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN_65_DSI_STRUCTURE_DATA_TYPE,
			0x00);

	/*PLL_EN set LOW - enable*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_PLL_EN, 0x01);
	HAL_Delay(10);

	/*SN65_reg_SOFT_RESET*/
	SN65_reg_i2c_write_byte(SN65_I2C_ADDR_WRITE, SN65_reg_SOFT_RESET, 0x01);
	HAL_Delay(10);

	return 1;
}

uint8_t SN65_reg_i2c_write_byte(uint8_t u8Address, uint8_t u8Offset,
		uint8_t u8Data) {
	HAL_StatusTypeDef status;

	status = HAL_I2C_Mem_Write(&hi2c1, u8Address, u8Offset, 1, &u8Data, 1,
			1000);
	if (status != 0x00U)
		return 1;
	else
		return 0;
}

uint8_t SN65_reg_i2c_read_byte(uint8_t u8Address, uint8_t u8Offset) {

	uint8_t read_data = 0;
	HAL_I2C_Mem_Read(&hi2c1, u8Address, u8Offset, 1, &read_data, 1, 1000);

	return read_data;
}

void MX_I2C1_Init(void) {
	GPIO_InitTypeDef GPIO_InitStruct;

	GPIO_InitStruct.Pin = I2C_SCL_PIN | I2C_SDA_PIN;
	GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
	GPIO_InitStruct.Pull = GPIO_PULLUP;
	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
	GPIO_InitStruct.Alternate = GPIO_AF1_I2C1;
	HAL_GPIO_Init(I2C_SCL_PORT, &GPIO_InitStruct);

	/* Peripheral clock enable */
	__HAL_RCC_I2C1_CLK_ENABLE();

	hi2c1.Instance = I2C1;
	hi2c1.Init.Timing = 0x00100E16;
	hi2c1.Init.OwnAddress1 = 0;
	hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
	hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
	hi2c1.Init.OwnAddress2 = 0;
	hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
	hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
	hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;

	HAL_I2C_Init(&hi2c1);
}

Best regards,

Mateusz

over 5 years ago

0 Ikechukwu Anyiam over 5 years ago

TI__Mastermind 35130 points

Hi Mateusz,

The DSI clock cannot be the same frequency as the LVDS clock. It needs to be faster so that the line time is the same on both sides. Please reference this video to understand how to configure the settings: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation

Let me know if you continue to have issues after referencing the video.

Regards,

I.K.

Interface

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SN65DSI83: SN65DSI83, Propiety initializaton, clock setting