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TPS65987D: HRESET pin characteristics

David Mckinney
Expert 6630 points
Part Number: TPS65987D
Other Parts Discussed in Thread: TPS65982D,

Can you confirm that the HRESET pin information is as shown in datasheet sections 6.1 Absolute Maximum Ratings for I/O Voltage and in sections 6.13 I/O characteristics, are as shown for the GPIO pins.

In the previous part, TPS65982D, the HRESET pin characteristics were shown in a separate table.  Is this pin now considered and characterized as a GPIO?

We want to confirm that the TPS65987D HReset can be driven by a 1.8V port and what timing need be applied to it, if different from the GPIO timing.

  • 0
    TI__Genius 12700 points

    Hi David,

    Yes, the HRESET pin information on the datasheet is correct, it's similar to a GPIO, so yes it can be driven by 1.8V. The difference from the TPS56982 HRESET to the TPS65987D is that for the newer PD controller, it will be more of a soft reset where upon boot up it will load the same configurations from the RAM before the reset instead of a hard reset and getting the configurations from the SPI FLASH. If you would like more of a hard reset you will need to use the 4CC command GAID.

    Thank you,

    Hari

  • 0 in reply to Hari Patel1
    TI__Expert 6630 points

    Hi Hari;

    Thank you for this clarification.  Are the HReset_High and HReset_Low times the same as the '982D[C] at 0.6mS min?

  • 0 in reply to David Mckinney
    TI__Genius 12700 points

    Hi David,

    I will consult with the team and get back to you by the end of the week on the timing.

    Thank you,

    Hari

  • 0 in reply to Hari Patel1
    TI__Mastermind 29995 points

    Hi David,

    Apologize for the late reply. Hari has moved to another team so I can help with this question.

    Do you have a TPS65987DEVM that you can use to test with? 

  • 0 in reply to Adam Mc Gaffin
    TI__Expert 6630 points

    Hi Adam;  Thank you for looking into this.

    I do not have an EVM to test this in the field.  Since they are looking for HRESET timing criteria like Minimum High to assert and minimum Low times to de-assert a RESET, it will be difficult to test in a field office.  We may have characterized this during initial test, but not included this information in the datasheet, like we did in the previous device ('82D)

    Please let me know.

  • 0 in reply to David Mckinney
    TI__Mastermind 29995 points

    Hey David,

    Recommend that you order an EVM as it serves as a good reference point when debugging customer systems.

    I programmed a TPS65987DEVM to where GPIO0 had an internal pull up that was enabled without event and had an initial value of 1. Meaning, once the PD controller was in normal operation and received the patch from the SPI Flash, it would pull that GPIO high. 

    For the test sequence, I pressed the reset button on the EVM whch would pull HRESET high, disabling the EVM and pulling low the GPIO. I would then release the button, deasserting HRESET and then eventually pulling up GPIO0. The disable and enable timings in respects to HRESET are below.