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SN65DSI86: Spec requirements for SN65DSI86 or right candidates

Dennis Oh
Prodigy 440 points
Part Number: SN65DSI86

 Hello,  

one of my customer is searching for  MIPI-to-eDP solution and the spec requirements from system as below ;    can SN65DSI86 meet them?  or do we have a better product to suggest?  

===============================================

1. Resolution : FHD@60Hz

2. Input I/F : mipi 4-lane

3. Output I/F : eDP 2-lane @ HBR (2.7Gbps)

4. ASSR support

5. Dimension : small size is preferred

6. Power consumption : low power consumption is preferred

7. Special Feature : MIPI M/N value auto setting (H/W or F/W) - not manual setting 

 detail about no. 7 :   there are multiple MIPI sources as input interface so, the driver should automatically detect & adjust the M/N value of MIPI clock accordingly.  it should be HW or FW controlled, not by manually software. 

=======================================================================

 Can SN65DSI86  support what customer needs ? ? 

 Thanks in adv. 

  • 0
    TI__Guru**** 166631 points

    DSI86 should able to support the FHD@60Hz resolution.

    For question #7

    To properly sample high-speed data received on the DSI interface, the DSIx6 implements a hardware mechanism, known as DSI_CLK_RANGE Estimator, to determine the DSI clock frequency. This hardware mechanism uses the REFCLK as a reference for calculating the DSI clock frequency. When the REFCLK_FREQ register correctly matching the REFCLK frequency, the DSI_CLK_RANGE Estimator will be able determine the DSIA and DSIB clock frequency. The DSI_CLK_RANGE Estimator requires a throw-away read (that is, read from address 0x00) before hardware will update CHA_DSI_CLK_RANGE and CHB_DSI_CLK_RANGE registers. Note that this first access may set some DSI error bits.

    In the cases where the system designer does not wish to use the DSI_CLK_RANGE Estimator, software can write the desired DSI Clock frequency to the CHA_DSI_CLK_RANGE and CHB_DSI_CLK_RANGE. Once these registers are written, the DSI_CLK_RANGE Estimator will be disabled and it becomes system software responsibility to make sure the CHA_DSI_CLK_RANGE and CHB_DSI_CLK_RANGE registers always reflect the actual DSI clock frequency.

    Thanks

    David